Method and apparatus for synchronizing internal state of frequency generators on a communications network

• US 20060056560A1
• Filed: 06/30/2005
• Published: 03/16/2006
• Est. Priority Date: 09/13/2004
• Status: Active Grant

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Ouellette, Michel, Aweya, James, Felske, Kent, Montuno, Delfin Y.
• Granted Patent: US 7,590,210 B2
• Time in Patent Office: Days
• US Class Current: 375/356
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H04J 3/0664 unidirectional timestamps

Abstract

A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.

Claims

1. A method of synchronizing a master clock and a slave clock, the master clock implementing a phase locked loop configured to synchronize an output signal generated by a master Digitally Controlled Frequency Selector (DCFS) with an input reference signal, the DCFS being configured to use a master DCFS clock signal independent of the reference frequency to generate the output signal, the method comprising the steps of:

monitoring the master DCFS clock signal; and

transmitting information associated with the master DCFS clock signal to the slave clock to enable the slave clock to synchronize operation of a slave local oscillator with the master DCFS clock signal.

2. The method of claim 1, further comprising the steps of determining a control word for the master DCFS and transmitting the control word from the master DCFS to the slave clock.

3. The method of claim 1, wherein the information associated with the master DCFS clock signal is a counter value forming a timestamp.

4. A slave clock, comprising:

a digitally controlled frequency selector configured to generate a synthesized output signal the frequency of which is selected by the input of a control word; and

a frequency adjustable local oscillator configured to input a reference signal to the digitally controlled frequency selector.

5. The slave clock of claim 4, wherein an operating frequency of the frequency adjustable local oscillator is determined using a phase locked loop.

6. The slave clock of claim 5, wherein the phase locked loop is configured to adjust the operating frequency of the frequency adjustable local oscillator by comparing a master oscillator timestamp difference associated with operation of a master clock signal with a slave timestamp difference associated with operation of frequency adjustable local oscillator.

7. The slave clock of claim 4, wherein the digitally controlled frequency selector is a digitally controlled oscillator comprising a counter and a comparator, and wherein the control word is used to set at least one of an initial value of the counter and a value of the comparator.

8. The slave clock of claim 7, wherein the frequency adjustable local oscillator is configured to output a signal, a frequency of which, is used to determine the frequency with which the counter is adjusted.

9. The slave clock of claim 8, wherein the slave clock comprises means to adjust the frequency of the frequency adjustable local oscillator to approximate a frequency of a local oscillator at a master clock.

10. The slave clock of claim 7, wherein the slave clock further comprises:

a timestamp generator configured to generate slave timestamps from the input to the digitally controlled frequency selector; and

circuitry configured to receive master timestamps associated with operation of an oscillator at a master clock and to compare differences in master timestamps with differences in slave timestamps.

11. The slave clock of claim 4, wherein the digitally controlled frequency selector is a direct digital synthesizer.

12. The slave clock of claim 12, wherein the direct digital synthesizer comprises a phase accumulator configured to accumulate an amount of phase set by the control word during each period of the input a reference signal.

13. A master clock, comprising:

a phase locked loop configured to synchronize a synthesized output signal generated by a digitally controlled frequency selector with a reference signal;

a control word generator configured to periodically collect a control word being used by the digitally controlled frequency selector to generate the synthesized output signal and to pass the collected control word to at least one slave clock; and

a timestamp generator configured to collect information from a master local oscillator associated with the digitally controlled frequency selector and to pass the collected information to the at least one slave clock.

14. The master clock of claim 13, wherein the timestamp generator is a counter configured to count pulses of the master local oscillator.

15. The master clock of claim 14, wherein the digitally controlled frequency selector is a digitally controlled oscillator comprising the master local oscillator, a counter and a comparator, the master local oscillator producing a clock signal that is used to control a frequency with which the counter is incremented.

16. The master clock of claim 15, wherein the control word generator is configured to collect information associated with at least one of a value of an initial value of the counter or a value of the comparator.

17. The master clock of claim 14, wherein the digitally controlled frequency selector is a direct digital synthesizer comprising the master local oscillator, a phase accumulator, and a phase to amplitude converter, and wherein the master local oscillator is configured to produce a clock signal that is used to control a frequency when a phase increment is added to the phase accumulator.

18. The master clock of claim 17, wherein the control word generator is configured to collect information associated with the phase increment.