Processes, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making
First Claim
1. An integrated circuit comprising:
- execute circuitry operable to execute at least part of an encryption process involving a set of data having numerousness N, the circuitry arranged to update at least first and second data concurrently in the set in a series of overlapping iterations followed by subsequent overlapping iterations in the series wherein at least one of the second data depends on the uncompleted processing of the first data; and
an assemblage of memory elements coupled to the execute circuitry having at least two read ports and at least two write ports operable for concurrent read and write, the elements having addresses, the number of memory elements being bounded in numerousness by the number N and sufficient to be utilized by the execute circuitry for updating the set of data for a subsequent iteration in the series.
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Accused Products
Abstract
A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line. The selector circuit (1412) responds to a state on a dirty bit line (db) to couple data bits related to the address bits themselves from the address line (1421) to the selector output (1412). Other circuits and methods of manufacture and operation are also disclosed.
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Citations
144 Claims
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1. An integrated circuit comprising:
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execute circuitry operable to execute at least part of an encryption process involving a set of data having numerousness N, the circuitry arranged to update at least first and second data concurrently in the set in a series of overlapping iterations followed by subsequent overlapping iterations in the series wherein at least one of the second data depends on the uncompleted processing of the first data; and
an assemblage of memory elements coupled to the execute circuitry having at least two read ports and at least two write ports operable for concurrent read and write, the elements having addresses, the number of memory elements being bounded in numerousness by the number N and sufficient to be utilized by the execute circuitry for updating the set of data for a subsequent iteration in the series. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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execute circuitry operable to execute at least part of an encryption process involving a set of data of a predetermined size, the circuitry arranged to process at least first and second threads concurrently in the set in a series of overlapping variable-length iterations; and
at least two memory units segregating the set of data, each of the memories coupled to the execute circuitry and having at least one read port and at least one write port operable for concurrent read and write, the locations having addresses, the predetermined size comprehending the total number of addresses occupied by the set of data utilized in operation of the execute circuitry in the memory units combined. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. Circuitry for use with a storage having storage locations for data and dirty bits accessible at addresses corresponding to addresses in the storage, the circuitry comprising:
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an address line for carrying address bits;
a data line for carrying data bits;
a dirty bit line for conveying a dirty bit set/reset state;
a selector circuit having a selector output selectively coupled to the address line, and to the data line, the selector circuit responsive to a state on the dirty bit line to couple data bits related to the address bits themselves from the address line to the selector output. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A method of operating circuitry for use with a storage having storage locations for data at a set of at least some addresses in the storage and for use with addressable dirty bits corresponding to the data, wherein each dirty bit has a dirty bit state being a set state or a reset state, wherein the method comprises
asserting a first address to retrieve the dirty bit state at that first address; - and
in response to a reset state as the dirty bit state retrieved, delivering to an output first data related to the first address instead of storage data at the first address. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55)
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56. An integrated circuit comprising:
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a first memory having a first read port and a first write port for concurrent read and write, the first memory having memory locations for data accessible by asserting respective addresses to the first memory through the first read port and the first write port;
a second memory having a second read port and a second write port for concurrent read and write, the second memory having memory locations for data accessible by asserting respective addresses to the second memory through the second read port and the second write port; and
address generation circuitry respectively coupled by address lines to said first memory and to said second memory and operable to generate address bits representative of odd and even addresses, said first memory responsive only to the even addresses and said second memory responsive only to the odd addresses. - View Dependent Claims (57, 58, 59, 60, 61, 62, 63, 64)
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65. A method of operating an integrated circuit comprising:
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concurrently reading and writing data in a first memory, the first memory having memory locations for data accessible by asserting respective addresses to the first memory through a first read port and a first write port;
concurrently reading and writing data in a second memory, the second memory having memory locations for data accessible by asserting respective addresses to the second memory through a second read port and a second write port; and
generating address bits representative of odd and even addresses, the first memory responsive only to the even addresses and the second memory responsive only to the odd addresses. - View Dependent Claims (66, 67, 68, 69, 70, 71)
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72. A process of making integrated circuits having operations of at least a portion of the integrated circuit definable by Case/Subcase tables, the process comprising
making at least a first state machine and a second state machine corresponding to a partition of the Case/SubCase tables into at least a first part and a second part.
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81. An integrated circuit comprising:
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a memory having memory locations for data accessible by asserting respective addresses to the memory;
a first register;
a second register;
read circuitry operable to read to the first register a first datum stored at a location in the memory represented by a first address;
an address circuit operable to generate a second address at which the first datum will be stored in said memory and a third address at which a second datum can be read from memory;
a comparison circuitry responsive to said address circuit when the third address is different from the second address to read the second datum to said second register from the third address in said memory, and when the third address is same as the second address then to copy the first datum to said second register as the second datum. - View Dependent Claims (82, 83)
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84. A process of resolving a dependency in an integrated circuit including a memory having memory locations for data accessible by asserting respective addresses to the memory, the process comprising:
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reading to a first register a first datum stored at a location in the memory represented by a first address;
generating a second address at which the first datum will be stored in the memory;
providing a third address at which a second datum can be read;
comparing the second address with the third address, and if different then reading the second datum to a second register from the third address in the memory, and if same then copying the first datum to the second register as the second datum. - View Dependent Claims (85, 86)
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87. An integrated circuit comprising:
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execute circuitry operable to execute at least part of a process involving a set of data, the circuitry arranged to process operations of setup and execution, each of the setup and execution including at least first and second threads concurrently in the set in a series of overlapping iterations; and
a state machine coupled to the execute circuitry, the state machine shared by the setup and execution iterations. - View Dependent Claims (88, 89, 90, 91, 92, 93, 94, 95, 96, 97)
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98. A method of operating an integrated circuit comprising:
executing at least part of a process including operations of setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by sharing a state machine for operations common to the setup and execution iterations. - View Dependent Claims (99, 100, 101, 102, 103, 104, 105, 106)
- 107. An article of manufacture comprising a substantially planar medium having physically established therein structures corresponding to operations of a process including operations of setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets.
- 120. A process of manufacturing a wireless communications device comprising establishing in the device operational features resulting from use of an article of manufacture comprising a substantially planar medium having physically established therein structures corresponding to operations of a process including operations of setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets.
- 128. A wireless communications device comprising a digital section and a radio frequency section, the digital section including circuitry having physically established therein structures implementing operations of setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets.
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141. A digital circuit comprising
a memory; -
a dirty bit array; and
an execution unit establishing maximum 256 (two hundred fifty six) bytes of S-Box in the memory and maximum 256 (two hundred fifty six) dirty bits in the dirty bit array corresponding to the S-Box, the execution unit having throughput exceeding 0.40 Bytes per cycle, the memory, dirty bit array, and execution unit together implemented in less than 20,000 (twenty thousand) gates. - View Dependent Claims (142, 143, 144)
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Specification