Methods of forming fuses using selective etching of capping layers

• US 20060057783A1
• Filed: 09/13/2005
• Published: 03/16/2006
• Est. Priority Date: 09/13/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yun, Cheol-ju, Kim, Bo-sung, Kang, Huck-jin
• Application Number:
  US11/225,789
• Publication Number:
  US 20060057783A1
• Time in Patent Office: Days
• US Class Current: 438/128
• CPC Class Codes: H01L 23/5258 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a fuse in a semiconductor device can be provided by selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse and removing the capping layer from the fuse to expose a fuse metal film thereunder.

Claims

1. A method of forming a fuse in a semiconductor device, the method comprising:

selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse; and

removing the capping layer from the fuse to expose a fuse metal film thereunder.

2. A method according to claim 1 wherein selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse further comprises:

selectively removing the inter-metal insulator to expose the fuse capping layer so that the capping layer protrudes from the inter-metal insulator around the fuse.

3. A method according to claim 1 wherein selectively removing comprises selectively dry-etching the inter-metal insulator relative the capping layer.

4. A method according to claim 1 wherein removing the capping layer comprises selectively wet-etching the capping layer relative to the inter-metal insulator around the fuse.

5. A method according to claim 4 wherein selectively wet-etching the capping layer relative to the inter-metal insulator around the fuse comprises selectively wet-etching the capping layer relative to the inter-metal insulator around the fuse to recess the fuse to beneath a surface of the inter-metal insulator around the fuse by about 1000 Angstroms.

6. A method according to claim 4 wherein the inter-metal insulator comprises an oxide and the capping layer comprises Ti, TiN, and/or Ti/TiN.

7. A method according to claim 4 wherein selectively wet-etching comprises wet-etching using an etching solution comprising H₂O₂ or a mixture of H₂O₂ and water.

8. A method according to claim 1 wherein the capping layer comprises Ti/TiN and a metal film thereunder comprises Al.

9. A method according to claim 4 wherein selectively wet-etching the capping layer relative to the inter-metal insulator around the fuse further comprises wet-etching using a solution of H₂O₂ at about 60 degrees Centigrade for about 11 minutes.

10. A method according to claim 9 wherein the solution of H₂O₂ further comprises a chemical solution that avoids etching of Ti and TiN.

11. A method according to claim 1 wherein removing the capping layer from the fuse to expose a fuse metal film thereunder further comprises wet-etching the capping layer to recess the fuse beneath a surface of the inter-metal insulator around the fuse to level sufficient to avoid contamination other fuses with debris from a laser cut of the fuse.

12. A method of forming a fuse in a semiconductor device, the method comprising:

selectively dry-etching an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse; and

selectively wet-etching the capping layer relative to the inter-metal insulator around the fuse to recess the fuse to beneath a surface of the inter-metal insulator around the fuse by about 1000 Angstroms using an etching solution comprising H₂O₂ or a mixture of H₂O₂ and water.

13. A method of forming a fuse in a semiconductor device, the method comprising:

forming an interconnection layer pattern on a first inter-metal insulator formed on a semiconductor, the interconnection layer comprising a metal film pattern and a capping layer pattern to provide a fuse;

forming a second inter-metal insulator covering the metal film pattern and the capping layer pattern on the first inter-metal insulator;

etching the second inter-metal insulator to expose the capping layer pattern formed in a fuse opening region; and

wet-etching the exposed capping layer pattern to expose the metal film pattern.

14. A method according to claim 13 wherein the capping layer pattern comprises a material having a sufficient wet etch selectively with respect to the second inter-metal insulator.

15. A method according to claim 14 wherein the second inter-metal insulator comprises an oxide and the capping layer pattern comprises Ti, TiN, and/or Ti/TiN.

16. A method according to claim 13 wherein the wet-etching is performed using an etching solution comprising H₂O₂ or a mixture of H₂O₂ and water.

17. A method according to claim 13 wherein the capping layer pattern and the metal film pattern is composed of materials having a sufficient etch selectivity with respect to each other.

18. A method according to claim 17 wherein the capping layer pattern comprises Ti/TiN and the metal film pattern comprises Al.

19. A method according to claim 13 wherein wet-etching comprises selectively wet-etching the capping layer pattern relative to the second inter-metal insulator around the fuse to recess the fuse to beneath a surface of the inter-metal insulator around the fuse by about 1000 Angstroms using an etching solution comprising H₂O₂ or a mixture of H₂O₂ and water.