Power estimation through power emulation

• US 20060058994A1
• Filed: 02/17/2005
• Published: 03/16/2006
• Est. Priority Date: 09/16/2004
• Status: Abandoned Application

• Current Assignee: NEC Laboratories America Inc (NEC Corporation)
• Original Assignee: NEC Laboratories America Inc (NEC Corporation)
• Inventors: Ravi, Srivaths, Raghunathan, Anand, Coburn, Joel
• Application Number:
  US11/059,839
• Publication Number:
  US 20060058994A1
• Time in Patent Office: Days
• US Class Current: 703/23
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

The time required to estimate the amount of power that will be consumed by a circuit under design is significantly speeded up. Specifically, the steps involved in power estimation (power model evaluation, aggregation) are implemented as power estimation circuitry that is added to the design of the functional circuit during circuit design. The resulting power-model-enhanced circuit is mapped onto a hardware emulation platform, one of whose outputs is a computation of the estimated power computed by the power estimation circuitry during the emulation. As compared to state-of-the-art commercial power estimation tools, speed-ups from around 10-fold to over 500-fold can be realized.

Claims

1. A method comprising

producing a circuit-implemented emulation that emulates a power-model-enhanced circuit, the power-model-enhanced circuit comprising a functional circuit and power estimation circuitry,

the power estimation circuitry being adapted to generate an estimate of the power consumption of functional circuitry of the functional circuit, the estimate being generated as a function of input signals applied to the circuit-implemented emulation when it is executed.

3. The method of claims 1 or 2 wherein the circuit-implemented emulation is a general purpose circuit that has been configured to emulate the power-model-enhanced circuit.

4. The method of claims 1 or 2 wherein the circuit-implemented emulation is an array of gates that have been interconnected in such a way as to emulate the power-model-enhanced circuit.

5. The method of claims 1 or 2 wherein the circuit-implemented emulation is a programmable gate array that is programmed in such a way as to emulate the power-model-enhanced circuit.

6. The method of claims 1 or 2 wherein the execution of the circuit-implemented emulation includes

applying a set of signals to a portion of the circuit-implemented emulation that emulates the functional circuitry, and

receiving an indication of said estimate from a portion of the circuit-implemented emulation that emulates the power estimation circuitry.

7. The method of claim 6 wherein the applied set of signals is generated using a test bench.

8. The method of claims 1 or 2 wherein the power estimation circuitry estimates the estimated power consumption as a function of a) said input signals and b) coefficients that characterize the power consumption characteristics of the functional circuitry.

9. The method of claim 8 wherein

the circuit-implemented emulation includes at least one block memory, and

at least ones of said coefficients are stored in said block memory.

10. The method of claim 8 wherein the functional circuitry includes at least first and second circuit components and wherein said power estimation circuitry includes first and second power model circuits associated with said first and second circuit components, respectively, the first and second power model circuits each being adapted to estimate the power consumption of the associated circuit component.

11. The method of claims 1 or 2 wherein the power estimation circuitry includes a least one power model circuit to which at least one of said input signals is applied, said power model circuit generating an estimate of the power consumption of at least a portion of the functional circuitry.

12. The method of claim 11 wherein

the functional circuitry includes two or more circuit components,

said at least one power model circuit estimates the power consumption of an individual one of the circuit components, and

said at least one power model circuit estimates the power consumption of the other circuit components as a function of the estimated power consumption of said individual one of said circuit components.

13. The method of claim 12 wherein the power consumption characteristics of each of said two or more circuit components meet a predetermined correlation criterion.

14. The method of claim 13 wherein the predetermined correlation criterion is that corresponding power consumption variables of said each of said two or more circuit components are linearly correlated to at least a predetermined extent.

15. The method of claim 11 wherein

the functional circuitry includes a cluster of two or more circuit components, and

said at least one power model circuit is adapted to estimate the power consumption of each of the circuit components of the cluster on a time-shared basis.

16. The method of claim 15 wherein said at least one power model circuit estimates the power consumption of at least one of the circuit components of the cluster at a lower rate than the rate of the input signals applied to that one of the circuit components.

17. The method of claims 1 or 2 wherein

the functional circuitry includes a plurality of clusters each formed of two or more circuit components, and

the power estimation circuitry includes power model circuits each associated with a respective one of the clusters, each power model circuit being adapted to estimate the power consumption of each of the circuit components of the associated cluster on a time-shared basis,

the clusters being formed in such a way that error in the power estimate made by the power estimation circuitry is less than if the clusters were to be formed in at least one other way.

18. The method of claim 17 wherein the clusters are formed in such a way that error in the power estimate made by the power estimation circuitry is less than if the clusters were to be formed in any other way.

19. The method of claim 17 wherein said at least one of the power model circuits estimates the power consumption of at least one of the circuit components of the associated cluster at a lower rate than the rate of the input signals applied to that one of the circuit components.

20. The method of claim 11 wherein said power model circuit estimates the power consumption of a combination of circuit components of the functional circuitry without explicitly taking account of at least one internal signal of that combination.

21. The method of claim 11 wherein said power model circuit includes at least one circuit resource having a function that is invoked two or more times successively during the power model circuit'"'"'s generation of said power estimate.

22. The method of claim 21 wherein said circuit resource is an adder.

23. The method of claims 1 or 2 wherein

the functional circuitry comprises at least first and second circuit components, and

the power estimation circuitry estimates the power consumption of said first and second circuit components at different associated sampling rates.

24. The method of claim 23 wherein

at least a first measure of the power consumption of said first circuit component is higher than the corresponding measure of the power consumption of said second circuit component, and

the sampling rate associated with said first circuit component is higher than the sampling rate associated with said second circuit component.

2. A circuit-implemented emulation of a power-model-enhanced circuit, the power-model-enhanced circuit comprising a functional circuit that is interconnected with power estimation circuitry, the power estimation circuitry being adapted to generate an estimate of the power consumption of functional circuitry of the functional circuit, the estimate being generated as a function of input signals applied to the circuit-implemented emulation when it is executed.

25. A method comprising

generating a description of a power-model-enhanced circuit, the power-model-enhanced circuit comprising a functional circuit and power estimation circuitry that is adapted to generate a succession of estimates of the power consumption of a plurality of components of the functional circuit in response to signals that are input to those components,

producing a circuit-implemented emulation of the power-model-enhanced circuit by configuring a configurable circuit system in response to the description of the power-model-enhanced circuit,

executing the circuit-implemented emulation with a test bench, and

obtaining the power consumption estimates from the emulated power estimation circuitry.

26. The method of claim 25 wherein

the functional circuit includes a cluster of two or more circuit components, and

the power model estimation circuitry is adapted to estimate the power consumption of each of the circuit components of the cluster on a time-shared basis.

27. The method of claim 25 wherein the description of the power-model-enhanced circuit is in a predetermined circuit-description language.

28. The method of claim 25 wherein said executing the circuit-implemented emulation with a test bench comprises applying a set of signals to the circuit-implemented emulation and receiving the power consumption estimates from the circuit-implemented emulation.

29. The method of claim 25 wherein the power estimation circuitry comprises a plurality of power model circuits, each of the power model circuits being associated with at least one of the functional circuit components, and each of the power model circuits being adapted to receive the same inputs as respective associated ones of the functional circuit components and, in response to a strobe signal received at a particular time, to generate an estimate of the power consumption of at least one of the associated functional circuit components at that particular time.

30. The method of claim 29 wherein each of the functional circuit components is operated in response to at least one clock signal applied thereto and wherein said strobe signal received by a power model circuit is generated as a function of at least one of the clock signals applied to at least one functional circuit component associated with that power model circuit.

31. The method of claim 30 each power model circuit generates said estimate as a function of a) its received inputs and b) coefficients that characterize the power consumption characteristics of the associated functional circuit components.

32. The method of claim 31 wherein

the configurable circuit system includes at least one block memory, and

at least ones of said coefficients are stored in said block memory.

33. The method of claim 29 wherein at least one of the power model circuits is associated with two or more of the functional circuit components and estimates the power consumption of at least one of the associated functional circuit components as a function of the estimated power consumption of less than all of them.

34. The method of claim 29 wherein at least one of the power model circuits is associated with two or more of the functional circuit components and estimates the power consumption of at least one of the associated functional circuit components as a function of the estimated power consumption of one of them.

35. The method of claim 33 wherein the power consumption characteristics of each of said two or more functional circuit components meet a predetermined correlation criterion.

36. The method of claim 35 wherein the predetermined correlation criterion is that corresponding power consumption variables of said each of said two or more functional circuit components are linearly correlated to at least a predetermined extent.

37. The method of claim 30 wherein

at least one of the power model circuits is adapted to estimate the power consumption of each of two or more of the functional circuit components on a time-shared basis.

38. The method of claim 37 wherein said at least one of the power model circuits estimates the power consumption of at least one of the two or more functional circuit components at a lower rate than the rate of the input signals applied to that one of the circuit components.

39. The method of claim 25 wherein

the functional circuitry includes a plurality of clusters each formed of two or more of the functional circuit components, and

the power estimation circuitry includes power model circuits each associated with a respective one of the clusters, each power model circuit being adapted to estimate the power consumption of each of the functional circuit components of the associated cluster on a time-shared basis,

the clusters being formed in such a way that any error in the power estimate made by the power estimation circuitry is less than if the clusters were to be formed in at least one other way.

40. The method of claim 39 wherein said at least one of the power model circuits estimates the power consumption of at least one of the functional circuit components of the associated cluster at a lower rate than the rate of the input signals applied to that one of the circuit components.

41. The method of claim 30 wherein at least one of said power model circuits estimates the power consumption of a combination of functional circuit components without explicitly taking account of at least one internal signal of that combination.

42. The method of claim 30 wherein at least one of said power model circuits includes at least one circuit resource having a function that is invoked two or more times successively during the power model circuit'"'"'s generation of an individual one of said power estimates.

43. The method of claim 42 wherein said circuit resource is an adder.

44. The method of claim 25 wherein

the power estimation circuitry estimates the power consumption of at least first and second functional circuit components at different associated sampling rates.

45. The method of claim 44 wherein

at least a first measure of the power consumption of said first functional circuit component is higher than the corresponding measure of the power consumption of said second functional circuit component, and

the sampling rate associated with said first functional circuit component is higher than the sampling rate associated with said second functional circuit component.