Apparatus and method for pipelined memory operations

• US 20060059299A1
• Filed: 11/08/2005
• Published: 03/16/2006
• Est. Priority Date: 10/10/1997
• Status: Active Grant

• Current Assignee: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, John B. Dillon, Mark A Horowitz, Nancy David Dillon, Richard M. Barth
• Original Assignee: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, John B. Dillon, Mark A Horowitz, Nancy David Dillon, Richard M. Barth
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Horowitz, Mark A., Dillon, John B., Dillon, Nancy David
• Granted Patent: US 7,330,951 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Claims

1. A memory device, comprising:

a dynamic memory core having memory cells arranged in rows and columns;

a plurality of external connections; and

interface circuitry coupled to said memory core and coupled to said external connections to receive row operation and column operation information, wherein said interface circuitry is configured to perform data transfers on said external connections in response to said column operation information, wherein said interface circuitry is configured to receive row operation information concurrently with data transfers on said external connections and wherein said interface circuitry is configured to receive column operation information concurrently with row operation information.