Solid state image pickup device and method for manufacturing the same

• US 20060060854A1
• Filed: 08/22/2005
• Published: 03/23/2006
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Mabuchi, Keiji, Wakano, Toshifumi, Matsubayashi, Kazunari, Nakashikiryo, Takashi
• Granted Patent: US 7,763,888 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

To reduce white spots by optimizing an impurity concentration of a p-type impurity doped region of a well contact, a size of a contact portion, a position of an n-type region serving as a photoelectric converter, and so on.

In a solid state image pickup device in which a semiconductor substrate 11 includes a pixel region where a plurality of pixels are arranged, each pixel including a photoelectric converter 21, and a pixel well 12 shared by the respective pixels, a well contact 14 supplying a reference voltage to the pixel well 12 includes: an electrode 15 supplying a reference voltage; a p-type impurity doped region 16 placed in a surface of the pixel well 12; and a contact portion 17 placed in the p-type impurity doped region 16 so as to be connected to the electrode 15 and having a higher concentration than the p-type impurity doped region 16. The p-type impurity doped region 16 is doped with at least a p-type impurity, with an impurity concentration of 1×10¹⁹ cm⁻³ or less.

Claims

1. A solid state image pickup device in which a semiconductor substrate includes a pixel region where a plurality of pixels are arranged, each pixel including a signal charge accumulating portion and a transistor, and a peripheral circuit region outside the pixel region,

the pixel region includes a pixel well of a first conductive type and a pixel well contact supplying a reference voltage to the pixel well, and

the peripheral circuit region includes a first peripheral well of a second conductive type and a MIS transistor of the first conductive type placed in a region of the first peripheral well,

the pixel well contact comprising:

an electrode supplying a reference voltage;

a first impurity doped region of the first conductive type placed in a surface of the pixel well; and

a contact portion of the first conductive type placed in the first impurity doped region so as to be connected to the electrode and having a higher concentration than the first impurity doped region,

wherein an impurity concentration of the first impurity doped region is lower than that of a source/drain of the MIS transistor.

2. The solid state image pickup device according to claim 1, wherein the first impurity doped region is doped with at least an impurity of the first conductive type and the impurity concentration thereof is 1×

10¹⁹ cm<sup>−

3</sup> or less.

3. The solid state image pickup device according to claim 1, wherein the first conductive type is a p-type and the second conductive type is an n-type.

4. The solid state image pickup device according to claim 1, wherein the signal charge accumulating portion is isolated from the contact portion.

5. The solid state image pickup device according to claim 1, wherein the signal charge accumulating portion includes a surface region of the first conductive type and an accumulating region of the second conductive type disposed under the surface region, and the surface region is included in the first impurity doped region.

6. The solid state image pickup device according to claim 5, wherein the signal charge accumulating portion extends to a portion under the contact portion.

7. The solid state image pickup device according to claim 1,

wherein the peripheral circuit region includes a second peripheral well of the first conductive type,

at least one of peripheral contacts supplying a reference voltage to the second peripheral well comprises:

a peripheral electrode supplying a reference voltage;

a second impurity doped region of the first conductive type placed in a surface of the second peripheral well; and

a contact portion of the first conductive type placed in the second impurity doped region so as to be connected to the peripheral electrode, and

an impurity concentration of the second impurity doped region is higher than that of the first impurity doped region.

8. A solid state image pickup device in which a semiconductor substrate includes a pixel region where a plurality of pixels are arranged, each pixel including a signal charge accumulating portion and a transistor, and a pixel well of a first conductive type shared by the respective pixels,

wherein the pixel region is provided with a pixel well contact supplying a reference voltage to the pixel well,

the pixel well contact comprises:

an electrode supplying a reference voltage;

a first impurity doped region of the first conductive type placed in a surface of the pixel well; and

a contact portion of the first conductive type placed in the first impurity doped region so as to be connected to the electrode and having a higher concentration than the first impurity doped region, and

the first impurity doped region is doped with at least an impurity of the first conductive type and the impurity concentration thereof is 1×

10¹⁹ cm<sup>−

3</sup> or less.

9. The solid state image pickup device according to claim 8, wherein the first conductive type is a p-type.

10. The solid state image pickup device according to claim 8, wherein the signal charge accumulating portion is isolated from the contact portion.

11. The solid state image pickup device according to claim 8, wherein the signal charge accumulating portion includes a surface region of the first conductive type and an accumulating region of the second conductive type disposed under the surface region, and part of the surface region is included in the first impurity doped region.

12. The solid state image pickup device according to claim 11, wherein the signal charge accumulating portion extends to a portion under the contact portion.

13. A method for manufacturing a solid state image pickup device in which a semiconductor substrate includes a pixel region where a plurality of pixels are arranged, each pixel including a signal charge accumulating portion and a transistor, and a pixel well of a first conductive type shared by the respective pixels, the method comprising:

a first step of forming a first impurity doped region by ion-implanting an impurity of the first conductive type to a surface of the semiconductor substrate together with the pixel well at a surface density of 1×

10¹⁴ cm<sup>−

2</sup> or less in total;

a second step of forming an interlayer film after the first step;

a third step of forming a hole for providing a contact electrode in the interlayer film on the first impurity doped region;

a fourth step of forming a contact portion by ion-implanting an impurity of the first conductive type through the hole; and

a fifth step of forming the contact electrode by filling the hole.

19. The method according to claim 13, wherein the first step includes ion implantation for forming a surface region of the first conductive type of the signal charge accumulating portion,

the method further comprising a step of performing ion implantation for forming a signal charge accumulating portion of a second conductive type under the surface region of the first conductive type.

20. The method according to claim 19, wherein the signal charge accumulating portion extends to a portion under the hole.

14. The method according to Clam 13, wherein the solid state image pickup device includes a peripheral circuit region outside the pixel region, the peripheral circuit region includes a first peripheral well of a second conductive type, and a region of the first peripheral well includes a MIS transistor of the first conductive type, the method further comprising:

a sixth step of performing ion implantation on a source/drain of the MIS transistor at a surface density of more than 1×

10¹⁴ cm<sup>−

2</sup> before the second step and after masking the first impurity doped region.

15. The method according to claim 14, wherein the solid state image pickup device includes a second peripheral well of the first conductive type in the peripheral circuit region, and

in the sixth step, ion implantation is also performed on a surface of a portion supplying a reference voltage to the second peripheral well so as to form a second impurity doped region.

16. The method according to claim 14, wherein the first conductive type is a p-type, the second conductive type is an n-type, and an ionic species used in the ion implantation in the fourth step is boron.

17. The method according to claim 16, wherein an ionic species used in the ion implantation in the sixth step is a p-type impurity except boron.

18. The method according to claim 17, wherein the ionic species used in the ion implantation in the sixth step is boron difluoride.

21. A method for manufacturing a solid state image pickup device in which a semiconductor substrate includes a pixel region where a plurality of pixels are arranged, each pixel including a signal charge accumulating portion and a transistor, and a p-type pixel well shared by the respective pixels, the method comprising:

a first step of forming the pixel well;

a second step of forming an interlayer film;

a third step of forming a hole for providing a contact electrode in the interlayer film at a position for a contact of the pixel well;

a fourth step of forming a contact portion by ion-implanting boron through the hole; and

a fifth step of forming the contact electrode by filling the hole.

22. The method according to claim 21, wherein the solid state image pickup device includes a peripheral circuit region outside the pixel region, the peripheral circuit region includes an n-type first peripheral well, and a region of the first peripheral well includes a p-type MIS transistor, the method further comprising:

a sixth step of forming a source/drain of the MIS transistor by ion-implanting a p-type impurity except boron.

23. The method according to claim 22, wherein an ion species used in the sixth step is boron difluoride.

24. The method according to claim 21, wherein the peripheral circuit region includes a p-type second peripheral well, the method further comprising:

a seventh step of ion-implanting a p-type impurity except boron to form a contact electrode in a hole of a peripheral contact, after forming the hole for providing the contact electrode of the peripheral contact in a step of forming the peripheral contact which supplies a reference voltage to the second peripheral well.