Methods of forming integrated circuit devices with metal-insulator-metal capacitors

• US 20060060907A1
• Filed: 11/14/2005
• Published: 03/23/2006
• Est. Priority Date: 06/26/2003
• Status: Abandoned Application

• Current Assignee: Gab-Jin Nam, Han-Mei Choi, Jae-Soon Lim, Ki-Chul Kim, Sung-Tae Kim, Thomas Jongwan Kwon, Young-Sun Kim
• Original Assignee: Gab-Jin Nam, Han-Mei Choi, Jae-Soon Lim, Ki-Chul Kim, Sung-Tae Kim, Thomas Jongwan Kwon, Young-Sun Kim
• Inventors: Choi, Han-Mei, Kim, Young-Sun, Lim, Jae-Soon, Kim, Ki-Chul, Nam, Gab-Jin, Kim, Sung-Tae, Kwon, Thomas Jongwan
• Application Number:
  US11/273,505
• Publication Number:
  US 20060060907A1
• Time in Patent Office: Days
• US Class Current: 257/303
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

Claims

1. A method of forming an integrated circuit capacitor, the method comprising:

forming a dielectric layer on a substrate;

forming a conductive contact plug extending through an opening in the dielectric layer to contact the substrate and including a widened pad portion extending onto the dielectric layer adjacent the opening and an ohmic pattern and a barrier pattern on the pad portion of the plug;

forming a concave first capacitor electrode on the barrier pattern and defining a cavity opening away from the substrate;

forming a capacitor dielectric layer conforming to a surface of the first capacitor electrode; and

forming a second capacitor electrode on the capacitor dielectric layer opposite the first capacitor electrode.

2. A method according to claim 1, wherein forming a conductive contact plug extending through an opening in the dielectric layer to contact the substrate and including a widened pad portion extending onto the dielectric layer adjacent the opening and an ohmic pattern and a barrier pattern on the pad portion of the plug comprises:

forming the opening in the dielectric layer;

forming a conductive layer on the dielectric layer and in the opening;

forming an ohmic layer on the conductive layer;

forming a barrier layer on the ohmic layer;

forming a metal etch stopper layer on the barrier layer;

forming a mask on the metal etch stopper layer; and

patterning the metal etch stopper layer, the barrier layer, the ohmic layer and the conductive layer using the mask to form the conductive contact plug, the ohmic pattern on the pad portion of the contact plug, the barrier pattern on the ohmic pattern, and a metal etch stopper pattern on the barrier pattern.

3. A method according to claim 2, wherein the conductive layer comprises polysilicon, wherein the ohmic layer comprises titanium silicide (TiSi_X), and wherein the barrier layer comprises at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAIN) and titanium aluminum nitride (TiAlN).

4. A method according to claim 2, wherein forming a concave first capacitor electrode comprises:

forming an etch stopper layer conforming to the metal etch stopper pattern, the barrier pattern, the ohmic pattern and the pad portion of the contact plug;

forming a mold layer on the etch stopper layer;

etching the mold layer to form an opening therein using the etch stopper layer as an etching stopper;

extending the opening through the etch stopper layer by etching the exposed portion of the etch stopper layer using the metal etch stopper pattern as an etching stopper;

forming a conductive layer on the mold layer and conforming to a sidewall of the opening through the mold layer and the etch stopper layer and the exposed portion of the metal etch stopper pattern; and

planarizing to form the first capacitor electrode.

5. A method according to claim 4, wherein the conductive layer comprises at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), rhodium (Rh), cobalt (Co) and nickel (Ni).

6. A method according to claim 4, wherein the mold layer comprises at least one material from a group including Hydrogen Silsesquioxane (HSQ), Boron Phosphorus Silicate Glass (BPSG), High density plasma (HDP) oxide, plasma enhanced tetraethyl orthosilicate (PETEOS), Undoped Silicate Glass (USG), Phosphorus Silicate Glass (PSG), plasma-enhanced (PE)-SiH₄ and aluminum oxide (Al₂O₃), wherein the etch stopper layer comprises at least one material from group including silicon nitride (Si₃N₄) and tantalum oxide (Ta₂O₅), and wherein the metal etch stopper layer comprises at least one material from a group including tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), rhodium (Rh), cobalt (Co) and nickel (Ni).

7. A method according to claim 1, further comprising forming a support layer on the dielectric layer and laterally abutting a base of the concave first capacitor electrode.

8. A method of forming an integrated circuit capacitor, the method comprising:

forming a dielectric layer on a substrate;

forming a conductive contact plug extending through an opening in the dielectric layer to contact the substrate and including a widened pad portion extending onto the dielectric layer adjacent the opening and stacked ohmic and barrier patterns disposed on the pad portion of the plug and having sidewalls substantially coplanar with a sidewall of the pad portion;

forming a first capacitor electrode on the barrier pattern;

forming a capacitor dielectric layer on the first capacitor electrode; and

forming a second capacitor electrode on the capacitor dielectric layer opposite the first capacitor electrode.

9. A method according to claim 8, wherein forming a conductive contact plug extending through an opening in the dielectric layer to contact the substrate and including a widened pad portion extending onto the dielectric layer adjacent the opening and stacked ohmic and barrier patterns disposed on the pad portion of the plug and having sidewalls substantially coplanar with a sidewall of the pad portion comprises:

forming an opening in the dielectric layer;

forming a conductive layer on the dielectric layer and in the opening;

forming an ohmic layer on the conductive layer;

forming a barrier layer on the ohmic layer;

forming a metal etch stopper layer on the barrier layer;

forming a mask on the metal etch stopper layer; and

patterning the metal etch stopper layer, the barrier layer, the ohmic layer and the conductive layer using the mask to form the conductive contact plug, the ohmic pattern on the pad portion of the contact plug, the barrier pattern on the ohmic pattern, and a metal etch stopper pattern on the barrier pattern.

10. A method according to claim 9, wherein the conductive layer comprises polysilicon, wherein the ohmic layer comprises titanium silicide (TiSi_X), and wherein the barrier layer comprises at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN) and titanium aluminum nitride (TiAlN).

11. A method according to claim 9, wherein forming a first capacitor electrode comprises:

forming an etch stopper layer conforming to the metal etch stopper pattern, the barrier pattern, the ohmic pattern and the pad portion of the contact plug;

forming a mold layer on the etch stopper layer;

etching the mold layer to form an opening therein using the etch stopper layer as an etching stopper;

extending the opening through the etch stopper layer by etching the exposed portion of the etch stopper layer using the metal etch stopper pattern as an etching stopper;

forming a conductive layer on the mold layer and conforming to a sidewall of the opening through the mold layer and the etch stopper layer and the exposed portion of the metal etch stopper pattern; and

planarizing to form the first capacitor electrode.

12. A method according to claim 11, wherein the conductive layer comprises at least one material from a group including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), rhodium (Rh), cobalt (Co) and nickel (Ni).

13. A method according to claim 11, wherein the mold layer comprises at least one material from a group including of Hydrogen Silsesquioxane (HSQ), Boron Phosphorus Silicate Glass (BPSG), High density plasma (HDP) oxide, plasma enhanced tetraethyl orthosilicate (PETEOS), Undoped Silicate Glass (USG), Phosphorus Silicate Glass (PSG), plasma-enhanced (PE)-SiH₄ and aluminum oxide (Al₂O₃), wherein the etch stopper layer comprises at least one material from a group including silicon nitride (Si₃N₄) and tantalum oxide (Ta₂O₅), and wherein the metal etch stopper layer comprises at least one material from a group including tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), rhodium (Rh), cobalt (Co) and nickel (Ni).