Power devices having trench-based source and gate electrodes

• US 20060060916A1
• Filed: 08/25/2005
• Published: 03/23/2006
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ma, Ling, Girdhar, Dev Alok
• Granted Patent: US 7,465,986 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.

Claims

1. A power semiconductor device, comprising:

a semiconductor body of a first conductivity type;

a plurality of gate trenches extending to a first depth within said semiconductor body;

a plurality of source trenches extending to a second depth within said semiconductor body, said second depth being greater than said first depth;

an insulated gate electrode within each of said plurality of gate trenches;

an insulated source electrode within each of said plurality of source trenches;

a channel region of a second conductivity type in said semiconductor body and having an etched surface adjacent to each of said plurality of source trenches;

a source contact contacting said source electrodes and contacting said channel region along said etched surfaces; and

wherein said plurality of gate trenches and said plurality of source trenches are arranged in a cellular design.

2. The device of claim 1, further comprising a drift region of said first conductivity type in said semiconductor body and beneath said channel region, wherein said drift region is doped in a monotonically increasing fashion away from said channel region.

3. The device of claim 1, wherein said insulated gate electrodes do not extend above a top surface of said semiconductor body

4. A power semiconductor device, comprising:

a semiconductor body having a drift region of a first conductivity type;

a plurality of gate trenches extending to a first depth within said semiconductor body;

a plurality of source trenches extending to a second depth within said semiconductor body and extending within said drift region, said second depth being greater than said first depth;

an insulated gate electrode within each of said plurality of gate trenches;

an insulated source electrode within each of said plurality of source trenches and extending within said drift region, each insulated source electrode having a decreasing width as it extends within said drift region; and

a source contact over an upper surface of said semiconductor body and contacting said source electrodes.

5. The device of claim 4, wherein side-walls of each of said plurality of source trenches slope inward substantially along said drift region, the sloping side-walls causing the decreasing width of said insulated source electrodes.

6. The device of claim 4, wherein each of said plurality of source trenches has a side-wall at least partially lined with an insulation layer, and wherein said insulation layers increase in thickness substantially along said drift region.

7. The device of claim 6, wherein said insulation layers increase in thickness in a stepwise fashion and wherein said source electrodes decrease in width in a stepwise fashion.

8. A power semiconductor device, comprising:

a semiconductor body of a first conductivity type;

a plurality of gate trenches within said semiconductor body;

a plurality of source trenches within said semiconductor body, wherein said plurality of gate trenches and said plurality of source trenches extend substantially to the same depth within said semiconductor body;

an insulated gate electrode within each of said plurality of gate trenches;

a source electrode within each of said plurality of source trenches; and

a source metal contact in contact with said insulated source electrodes.

9. The device of claim 8, wherein said plurality of gate trenches and said plurality of source trenches are arranged in a cellular design.

10. The device of claim 8, further comprising a drain region of the first conductivity type in said semiconductor body, and wherein said plurality of source trenches and said plurality of gate trenches extend within said drain region.

11. The device of claim 8, further comprising a drift region, a buffer region, and a drain region in said semiconductor body, each of said first conductivity type, wherein said drift region is disposed over said buffer region and said buffer region is disposed over said drain region.

12. The device of claim 11, wherein said plurality of source trenches and said plurality of gate trenches extend within said buffer region.

13. The device of claim 8, further comprising a drift region of said first conductivity type in said semiconductor body, wherein said drift region is doped in a monotonically increasing fashion from a top towards a bottom of said drift region.

14. The device of claim 8, wherein each source electrode and each gate electrode includes a free end that extends above a surface of said semiconductor body.

15. The device of claim 14, further comprising a silicide contact at said free end of each gate electrode and each source electrode.

16. The device of claim 8, further comprising:

a drift region of said first conductivity type in said semiconductor body; and

wherein said plurality of source trenches and said plurality of gate trenches extend within said drift region and include side-walls that slope inward substantially along said drift region

17. The device of claim 16, further comprising:

a channel region of a second conductivity type in said semiconductor body and disposed above said drift region; and

wherein said side-walls of said plurality of source trenches and said plurality of gate trenches extend through said channel region at a substantially vertical angle.

18. The device of claim 8, further comprising a plurality of Schottky contacts on said semiconductor body, each Schottky contact being between adjacent source and gate trenches.

19. The device of claim 8, further comprising a plurality of P-N diodes, each P-N diode being formed between adjacent source trenches.

20. The device of claim 8, wherein each gate electrode extends to a first depth within its respective gate trench and each source electrode extends to a second depth within its respective source trench, said second depth being greater than said first depth.

21. The device of claim 20, further comprising a gate insulation plug within each of said plurality of gate trenches, each insulation plug being disposed below the respective gate electrode.

22. The device of claim 20, further comprising a floating gate electrode within each of said plurality of gate trenches.

23. The device of claim 20, further comprising a second gate electrode within each of said plurality of gate trenches, said second gate electrode and said insulated gate electrode within each gate trench being electrically connected through a gate contact.

24. The device of claim 20, further comprising:

a drift region of said first conductivity type in said semiconductor body, wherein said plurality of source trenches and said plurality of gate trenches extend within said drift region; and

an insulation layer lining at least a portion of a side-wall of each of said plurality of source trenches, wherein each insulation layer has an increasing thickness substantially along said drift region.

25. The device of claim 24, wherein each source electrode extends within said drift region and has a decreasing width as it extends within said drift region.

26. The device of claim 24, wherein said insulation layers increase in thickness in a stepwise fashion.

27. The device of claim 26, wherein each source electrode extends within said drift region and decreases in width in a stepwise fashion as it extends within said drift region.

28. The device of claim 20, further comprising at least a second source electrode within each of said plurality of source trenches, each of said at least second source electrodes being in contact with said source contact.

29. The device of claim 28, wherein each of said at least second source electrodes extends substantially to said first depth within its respective source trench.

30. The device of claim 20, further comprising:

a source insulation layer lining at least a portion of a side-wall of each of said plurality of source trenches; and

a gate insulation layer lining at least a portion of a side-wall of each of said plurality of gate trenches; and

wherein a side-wall thickness of said source insulation layer is thicker than a side-wall thickness of said gate insulation layer.

31. The device of claim 8, further comprising:

a drift region of said first conductivity type in said semiconductor body;

a channel region of a second conductivity type in said semiconductor body and disposed over said drift region, wherein said plurality of source trenches and said plurality of gate trenches extend within said channel region and said drift region;

a first implant region of said second conductivity type formed within said drift region at a bottom of each of said plurality of source trenches;

a second implant region of said first conductivity type formed within said drift region at a bottom of each of said plurality of gate trenches; and

wherein said source contact metal fills each of said plurality of source trenches, thereby forming said source electrodes.

32. The device of claim 8, further comprising:

a drift region of said first conductivity type in said semiconductor body;

a channel region of a second conductivity type in said semiconductor body and disposed above said drift region;

wherein each gate electrode and each source electrode extends within its respective trench along said channel region and along said drift region; and

wherein each gate electrode and each source electrode has a first width substantially along said channel region and a second width substantially along said drift region, said first width being greater than said second width.

33. The device of claim 8, further comprising:

a drift region of said first conductivity type in said semiconductor body;

a channel region of a second conductivity type in said semiconductor body and disposed above said drift region;

wherein each gate electrode and each source electrode extends within its respective trench along said channel region and along said drift region;

wherein each gate electrode has a first width substantially along said channel region and a second width substantially along said drift region, said first width being greater than said second width; and

wherein each source electrode has a substantially uniform width less than said first width.

34. The device of claim 8, further comprising:

a plurality of varying length insulated gate electrodes within each of said plurality of gate trenches; and

a plurality of varying length insulated source electrodes within each of said plurality of source trenches, each of said plurality of source electrodes being in contact with said source contact.

35. A power semiconductor device, comprising:

a semiconductor body of a first conductivity type;

a plurality of trenches within said semiconductor body;

a plurality of insulated gate electrodes within each of said plurality of trenches, said plurality of gate electrodes within a given trench extending vertically downward within the trench; and

an insulation layer lining side-wall and bottom surfaces of each of said plurality of trenches.

36. The device of claim 35, wherein said plurality of gate electrodes within a given trench are connected to a common gate electrode.

37. The device of claim 35, wherein said plurality of gate electrodes within a given trench are of varying length.

38. The device of claim 35, further comprising:

an insulated source electrode extending vertically downward within each of said plurality of trenches; and

a source contact contacting said source electrodes.

39. The device of claim 38, wherein for each of said plurality of trenches said insulated source electrode extends between said plurality of insulated gate electrodes and extends to a greater depth than said plurality of insulated gate electrodes.