Atomic layer deposition of high dielectric constant gate dielectrics

• US 20060060930A1
• Filed: 09/17/2004
• Published: 03/23/2006
• Est. Priority Date: 09/17/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman, Kuhn, Markus, Boyd, Clifford W.
• Application Number:
  US10/943,693
• Publication Number:
  US 20060060930A1
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Gate dielectrics formed of silicates of hafnium or zirconium dioxide may be formed by atomic layer deposition. The precursors for the atomic layer deposition may include an oxidant, a silicate precursor, and a zirconium or hafnium precursor.

Claims

1. A method comprising:

forming a silicate of zirconium or hafnium dioxide by applying pulses of oxidant, a silicon precursor, and a zirconium or hafnium precursor to an atomic layer deposition chamber.

2. The method of claim 1 including exposing a wafer to successive pulses of silicon precursor, oxidant, and zirconium or hafnium precursor and oxidant.

3. The method of claim 2 including repeatedly providing a sequence of pulses of oxidant, silicon precursor, and zirconium or hafnium precursor.

4. The method of claim 2 including successively providing a sequence of pulses, in order, of oxidant, silicate precursor, zirconium, or hafnium precursor and oxidant.

5. The method of claim 4 including providing said pulses in the sequence of oxidant, silicate precursor, zirconium, or hafnium precursor and oxidant and repeating said sequence until the desired thickness of silicate is formed.

6. The method of claim 1 including forming a metal gate electrode over said silicate.

7. The method of claim 1 including forming a polysilicon gate electrode over said silicate.

8. The method of claim 1 including forming a source and drain.

9. The method of claim 1 including purging after each pulse.

10. A semiconductor structure comprising:

a stack of monolayers of hafnium silicate.

11. The structure of claim 10 wherein said stack forms a gate dielectric.

12. The structure of claim 11 including a metal gate on said stack.

13. The structure of claim 11 including a polysilicon gate on said stack.

14. A semiconductor structure comprising:

a series of stacked monolayers of zirconium silicate.

15. The structure of claim 14 wherein said stack forms a gate dielectric.

16. The structure of claim 15 including a metal gate on said stack.

17. The structure of claim 15 including a polysilicon gate on said stack.

18. A semiconductor structure comprising:

a substrate;

a gate dielectric formed of monolayers of zirconium or hafnium silicate; and

a gate electrode over said monolayers.

19. The structure of claim 18 wherein said gate electrode is formed of polysilicon.

20. The structure of claim 19 wherein said gate electrode is formed of metal.