Semiconductor device package

• US 20060060953A1
• Filed: 09/20/2004
• Published: 03/23/2006
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Kim, KiDon, Lee, JunHong, Yang, JunYoung, Han, JongHo
• Granted Patent: US 7,327,015 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/045 the other leads having an insulating passage through the base
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A semiconductor device package includes a semiconductor device mounted to a substrate, a wall erected around the semiconductor device with a height taller than the height of the semiconductor device, at least one metal member provided in the wall or against the wall; and a lid secured to the metal member. The metal member and the lid enclose substantially the semiconductor device for providing electromagnetic interference shielding.

Claims

1. A semiconductor device package comprising:

a substrate;

a semiconductor device mounted to the substrate and electrically coupled to the substrate;

a wall erected around the semiconductor device with a height taller than the height of the semiconductor device;

at least one metal member provided in the wall or against the wall; and

a lid secured to the metal member,

wherein the metal member and the lid enclose substantially the semiconductor device for providing electromagnetic interference shielding.

2. The semiconductor device package as claimed in claim 1, wherein the lid is a metal plate or a film with a conductive coating thereon.

3. The semiconductor device package as claimed in claim 1, wherein the metal member is connected to ground potential.

4. The semiconductor device package as claimed in claim 1, wherein the metal member is a metal ring.

5. The semiconductor device package as claimed in claim 1, wherein the metal member comprises a plurality of metal bars arranged around the semiconductor device.

6. The semiconductor device package as claimed in claim 1, wherein the metal member extends from the wall into the substrate.

7. The semiconductor device package as claimed in claim 1, wherein the substrate is an organic substrate or a ceramic substrate.

8. The semiconductor device package as claimed in claim 1, wherein the wall is integrally formed with the substrate.

9. The semiconductor device package as claimed in claim 1, wherein the lid is secured to the metal member by a soldering interface.

10. The semiconductor device package as claimed in claim 1, further comprising a solder layer or a black-oxidation layer formed on the lid.

11. A semiconductor device package comprising:

a substrate;

a semiconductor device mounted to the substrate and electrically coupled to the substrate;

at least one metal member provided in the substrate; and

a metal cover secured to the metal member thereby enclosing substantially the semiconductor device for providing electromagnetic interference shielding.

12. The semiconductor device package as claimed in claim 11, wherein the metal member extends from an upper surface to a lower surface of the substrate.

13. The semiconductor device package as claimed in claim 11, wherein the metal member is connected to ground potential.

14. The semiconductor device package as claimed in claim 11, wherein the metal member is a metal ring.

15. The semiconductor device package as claimed in claim 11, wherein the metal member comprises a plurality of metal bars arranged around the semiconductor device.

16. The semiconductor device package as claimed in claim 11, wherein the substrate is an organic substrate or a ceramic substrate.

17. The semiconductor device package as claimed in claim 11, the metal cover is secured to the metal member by a soldering interface.

18. The semiconductor device package as claimed in claim 11, wherein the metal cover has a top portion and a side wall extending from the top portion, and the top portion of the metal cover comprises a solder layer or a black-oxidation layer formed thereon.

19. A semiconductor device package comprising:

a substrate having a top portion and a bottom portion; and

a semiconductor device mounted to the top portion of the substrate and electrically coupled to the substrate; and

a metal cover having a base portion and a side wall extending from the base portion, the metal cover being secured to the substrate for providing electromagnetic interference shielding,

wherein the size of the side wall is slightly larger than the size of the top portion of the substrate to enable the top portion of the substrate to be received within the metal cover, and the side wall of the metal cover abuts the bottom portion of the substrate when the top portion of the substrate is received within the metal cover.

20. The semiconductor device package as claimed in claim 19, wherein the substrate is an organic substrate or a ceramic substrate.

21. The semiconductor device package as claimed in claim 19, further comprising a solder layer or a black-oxidation layer formed on the base portion of the metal cover.