Chip structure

• US 20060060961A1
• Filed: 07/11/2005
• Published: 03/23/2006
• Est. Priority Date: 07/09/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chiu-Ming
• Granted Patent: US 8,022,544 B2
• Time in Patent Office: Days
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13028 the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.

Claims

1. A semiconductor chip or wafer comprising:

a semiconductor substrate;

an interconnecting metallization structure over said semiconductor substrate;

a passivation layer over said interconnecting metallization structure;

a circuit layer over said passivation layer; and

a bump on said circuit layer, wherein a topmost metal layer of said bump has a melting point greater than 185 centigrade degrees.

2. The semiconductor chip or wafer of claim 1, wherein said topmost metal layer comprises gold with greater than 90 weight percent, and said topmost metal layer has a thickness of between 7 μ

m and 30 μ

m.

3. The semiconductor chip or wafer of claim 1, wherein said topmost metal layer comprises a lead-free solder material.

4. The semiconductor chip or wafer of claim 1, wherein said melting point greater than 400 centigrade degrees

5. The semiconductor chip or wafer of claim 1, wherein said circuit layer comprises a metal layer comprising gold with greater than 90 weight percent and having a thickness of between 2 μ

m and 30 μ

m.

6. A semiconductor chip or wafer comprising:

a semiconductor substrate;

an interconnecting metallization structure over said semiconductor substrate;

a passivation layer over said interconnecting metallization structure, wherein an opening is in said passivation layer and exposes a contact point of said interconnecting metallization structure;

a circuit layer over said passivation layer; and

a bump on said contact point.

7. The semiconductor chip or wafer of claim 6, wherein said bump comprises a topmost metal layer having a melting point greater than 400 centigrade degrees.

8. The semiconductor chip or wafer of claim 6, wherein said bump comprises a topmost metal layer comprising gold with greater than 90 weight percent and having a thickness of between 7 μ

m and 30 μ

m.

9. The semiconductor chip or wafer of claim 6, wherein said topmost metal layer comprises a lead-free solder material.

10. The semiconductor chip or wafer of claim 6, wherein said circuit layer comprising a metal layer comprising gold with greater than 90 weight percent and having a thickness of between 2 μ

m and 30 μ

m.

11. A semiconductor chip or wafer comprising:

a semiconductor substrate;

an interconnecting metallization structure over said semiconductor substrate;

a passivation layer over said interconnecting metallization structure, wherein an opening is in said passivation layer and exposes a contact point of said interconnecting metallization structure; and

a bump over said passivation layer or over said contact point, wherein said bump comprises a topmost metal layer with a melting point greater than 350 centigrade degrees and with gold ranging from 0 weight percent to 90 weight percent.

12. The semiconductor chip or wafer of claim 11, wherein said melting point greater than 400 centigrade degrees

13. The semiconductor chip or wafer of claim 11 further comprising a circuit layer over said passivation layer, wherein said bump is on said circuit layer.

14. The semiconductor chip or wafer of claim 11 further comprising a circuit layer over said passivation layer, wherein said bump is on said contact point.