Semiconductor device packaged into chip size and manufacturing method thereof

• US 20060060984A1
• Filed: 09/14/2005
• Published: 03/23/2006
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Mihara, Ichiro, Wakabayashi, Takeshi
• Granted Patent: US 7,417,330 B2
• Time in Patent Office: Days
• US Class Current: 257/780
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an integrated circuit and at least one connection pad;

at least one external connection electrode electrically connected with the connection pad;

a first sealing material provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm; and

a second sealing material provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

2. The semiconductor device according to claim 1, wherein a thermal expansion coefficient of the first sealing film is less than 20 ppm/°

C., and a thermal expansion coefficient of the second sealing film is not smaller than 20 ppm/°

C.

3. The semiconductor device according to claim 1, wherein the second sealing film is provided on both the lower surface and the peripheral side surface of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein the second sealing film is further provided on a peripheral side surface of the first sealing material.

5. The semiconductor device according to claim 1, wherein said at least one external connection electrode is a columnar electrode.

6. The semiconductor device according to claim 5, wherein the columnar electrode has a height of 80 to 150 μ

m.

7. The semiconductor device according to claim 1, wherein a solder ball is provided on the external connection electrode.

8. The semiconductor device according to claim 1, further comprising at least one wiring which electrically connects-the connection pad with the external connection electrode.

9. The semiconductor device according to claim 1, further comprising a protection film interposed between the connection pad and the wiring.

10. A semiconductor device comprising:

a semiconductor substrate having an integrated circuit and a plurality of connection pads;

a protection film which has opening portions through which the respective connection pads are exposed and is provided on the semiconductor substrate;

a plurality of wirings which are connected with one of the connection pads and have connection pad portions each of which is formed on the protection film;

a plurality of external connection electrodes provided on the connection pad portions of the wirings;

a first sealing material provided on the semiconductor substrate around the external connection electrodes, each impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the first sealing material being not greater than 10 ppm; and

a second sealing material provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

11. The semiconductor device according to claim 10, wherein the second sealing film is provided on both the lower surface and the peripheral side surface of the semiconductor substrate.

12. The semiconductor device according to claim 10, wherein the second sealing film is further provided on a peripheral side surface of the first sealing material.

13. A manufacturing method of a semiconductor device comprising:

preparing a semiconductor substrate in a wafer state which has a plurality of connection pads and a plurality of integrated circuits;

forming a plurality of external connection electrodes on the semiconductor substrate in the wafer state;

forming a first sealing film made of a first sealing material on the semiconductor substrate around the external connection electrodes, the first sealing material having each impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion which is not greater than 10 ppm;

cutting the semiconductor substrate in the wafer state and the first sealing film to form grooves having a predetermined width which divide the semiconductor substrate into each semiconductor substrate;

forming a second sealing film consisting of a second sealing material on a lower surface of the semiconductor substrates including the inside of the grooves, the second sealing material having a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion which is not smaller than 100 ppm; and

cutting the second sealing film formed in the grooves on the inner side of the grooves having the predetermined width in order to divide the semiconductor substrate in the wafer state into the plurality of semiconductor substrates each having the integrated circuit and connection pad.

14. The manufacturing method of a semiconductor device according to claim 13, wherein forming the second sealing film on the lower surface of the semiconductor substrate in the wafer state including the inside of the grooves is based on one of a screen printing method, a spin coat method and a die coat method.

15. The manufacturing method of a semiconductor device according to claim 13, further comprising attaching a film on a surface of the first sealing film before forming the grooves having the predetermined width.

16. The manufacturing method of a semiconductor device according to claim 15, further comprising peeling the film attached on the surface of the first sealing film from the surface of the first sealing film after forming the second sealing film on the lower surface of the semiconductor substrate in the wafer state including the inside of the grooves.

17. The manufacturing method of a semiconductor device according to claim 15, wherein forming the grooves having the predetermined width has forming to an intermediate point in a thickness direction of the film attached on the surface of the first sealing film, and forming the second sealing film consisting of the second sealing material on the lower surface of the semiconductor substrates including the inside of the groove includes forming a part of the second sealing film formed in the groove to protrude from the surface of the first sealing film.

18. The manufacturing method of a semiconductor device according to claim 16, comprising removing the part of the second sealing film protruding from the surface of the first sealing film so that the surfaces of the first sealing film and the second sealing film are set on the same level after peeling the film.

19. The manufacturing method of a semiconductor device according to claim 16, comprising attaching a second film on the second sealing film formed on the lower surface of the semiconductor substrates before cutting the second sealing film formed in the grooves on the inner side of the grooves having the predetermined width.

20. A manufacturing method of a semiconductor device comprising:

preparing a semiconductor substrate in a wafer state which has a plurality of connection pads and a plurality of integrated circuits;

forming a plurality of external connection electrodes on the semiconductor substrate in the wafer state;

forming a first sealing film made of a first sealing material on the semiconductor substrate in the wafer state around the external connection electrodes, the first sealing material having each impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion which is not greater than 10 ppm;

attaching a lower surface of the semiconductor substrate in the wafer state on a first film;

cutting to an intermediate point of the first film, the semiconductor substrate in the wafer state and the first sealing film in a thickness direction to form grooves;

attaching a second film on an upper surface of the first sealing film and peeling the first film from the lower surface of the semiconductor substrate in the wafer state;

forming a second sealing film consisting of a second sealing material on the lower surface of the semiconductor substrate in the wafer state and the inside of the grooves, the second sealing material having a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion which is not smaller than 100 ppm; and

cutting the second sealing film formed in the grooves on the inner side of the grooves having the predetermined width to divide the semiconductor substrate in the wafer state into the plurality of semiconductor substrates each having the integrated circuit and connection pad.