High-speed differential logic buffer

• US 20060061391A1
• Filed: 09/20/2004
• Published: 03/23/2006
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Tam, Kimo Y. F.
• Granted Patent: US 7,236,011 B2
• Time in Patent Office: Days
• US Class Current: 326/115
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence

Abstract

A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.

Claims

1. A circuit for a high speed digital buffer, the circuit comprising:

an active load circuit connected to an output of a high speed digital buffer and loading the buffer output with an active transinductance stage having a complex output impedance.

2. A circuit according to claim 1, wherein the digital buffer is a current mode logic circuit.

3. A circuit according to claim 1, wherein the digital buffer includes a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs.

4. A circuit according to claim 3, wherein the active load circuit further comprises:

for each differential output, an active device coupled so as to form a differential load circuit.

5. A circuit according to claim 4, further comprising:

for each active device, a gate impedance setting resistance coupled between a device voltage source and a device control terminal.

6. A circuit according to claim 4, wherein the active devices are medium threshold voltage devices.

7. A circuit according to claim 6, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

8. A circuit according to claim 7, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

9. A circuit according to claim 4, wherein the active devices are low threshold voltage devices.

10. A circuit according to claim 9, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

11. A circuit according to claim 10, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

12. A circuit according to claim 4, further comprising:

a trickle current arrangement coupling the differential outputs to each other to allow a trickle flow of current.

13. A circuit according to claim 4, further comprising:

for each differential output, a trickle current arrangement coupled to a device supply voltage to allow a trickle flow of current.

14. A circuit according to claim 4, further comprising:

for each differential output, a series damping resistance coupling the output to the associated active load device.

15. A circuit according to claim 1, further comprising:

for each device, an auxiliary drain current resistance which provides a load current path for a preceding circuit stage.

16. A circuit according to claim 1, wherein the digital buffer is a clock signal buffer.

17. A circuit according to claim 1, wherein the digital buffer is a data signal buffer.

18. A buffer containing an active load circuit according to claim 1.

19. A crosspoint switch containing an active load circuit according to claim 1.

20. A method for loading a high speed digital buffer, the method comprising:

coupling an active load circuit to an output of a high speed digital buffer so as to load the buffer output with an active transinductance stage having a complex output impedance.

21. A method according to claim 20, wherein the digital buffer is a current mode logic circuit.

22. A method according to claim 20, wherein the digital buffer includes a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs.

23. A method according to claim 22, wherein the active load circuit includes two active devices coupled to the differential outputs so as to form a differential load circuit.

24. A method according to claim 23, further comprising:

for each active device, coupling a gate impedance setting resistance between a device voltage source and a device control terminal.

25. A method according to claim 23, wherein the active devices are medium threshold voltage devices.

26. A method according to claim 25, further comprising:

isolating and biasing a back gate of each active device to a potential near a device supply voltage.

27. A method according to claim 26, further comprising:

coupling a back gate supply diode to a device supply voltage to provide the potential for each back gate.

28. A method according to claim 23, wherein the active devices are low threshold voltage devices.

29. A method according to claim 28, further comprising:

isolating and biasing a back gate of each active device to a potential near a device supply voltage.

30. A method according to claim 29, further comprising:

coupling a back gate supply diode to a device supply voltage to provide the potential for each back gate.

31. A method according to claim 23, further comprising:

coupling a trickle current resistance between the differential outputs and a device supply voltage to allow a trickle flow of current.

32. A method according to claim 23, further comprising:

for each differential input, coupling an input load resistance between the input and a device supply voltage.

33. A method according to claim 20, further comprising:

providing an auxiliary drain current resistance to present a load current path for a preceding circuit stage.

34. A method according to claim 20, wherein the digital buffer is a clock signal buffer.

35. A method according to claim 20, wherein the digital buffer is a data signal buffer.

36. A buffer adapted to use a method for loading a high speed digital buffer according to claim 20.

37. A crosspoint switch adapted to use a method for loading a high speed digital buffer according to claim 20.

38. A circuit for high speed digital data, the circuit comprising:

a first active load device having an input terminal coupled to an output of a first digital buffer, the first active load device loading the buffer output with an active transinductance stage having a complex output impedance, the first active load device further including an output terminal coupled to a device supply voltage; and

a second active load device having an input terminal coupled to an output of a second digital buffer, the second active load device loading the buffer output with an active transinductance stage having a complex output impedance, the second active load device further including a control terminal circuit which controls gain of the second active device;

wherein the second digital buffer includes an input which is coupled to the output of the first digital buffer; and

wherein the output terminal of the first active load device is coupled to the control terminal circuit of the second active load device.

39. A circuit according to claim 38, wherein the digital buffers are current mode logic circuits.

40. A circuit according to claim 38, wherein each digital buffer includes a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs.

41. A circuit according to claim 40, further comprising:

for each differential output of each active device, an active device coupled so as to form a differential load circuit.

42. A circuit according to claim 41, further comprising:

for each active device, a gate impedance setting resistance coupled between a device voltage source and a device control terminal.

43. A circuit according to claim 38, wherein the active devices are medium threshold voltage devices.

44. A circuit according to claim 43, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

45. A circuit according to claim 44, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

46. A circuit according to claim 38, wherein the active devices are low threshold voltage devices.

47. A circuit according to claim 46, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

48. A circuit according to claim 47, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

49. A circuit according to claim 38, further comprising:

a trickle current arrangement for each buffer, coupling the differential outputs to each other to allow a trickle flow of current.

50. A circuit according to claim 38, further comprising:

for each differential output, a trickle current arrangement coupled to a device supply voltage to allow a trickle flow of current.

51. A circuit according to claim 38, further comprising:

for each differential output, a series damping resistance coupling the output to the associated active load device.

52. A circuit according to claim 38, further comprising:

for each active load device, an auxiliary drain current resistance which provides a load current path for a preceding circuit stage.

53. A circuit according to claim 38, wherein the digital buffers are clock signal buffers.

54. A circuit according to claim 38, wherein the digital buffers are data signal buffers.

55. A crosspoint switch containing an active load circuit according to claim 38.

56. A method for loading a high speed digital data circuit, the method comprising:

providing a first active load device including;

i. coupling an input terminal of the first active load device to an output of a first digital buffer so as to load the buffer output with an active transinductance stage having a complex output impedance, and

ii. coupling an output terminal of the first active load device to a device supply voltage; and

providing a second active load device including;

i. coupling an input terminal of the second active load device to an output of a second digital buffer so as to load the buffer output with an active transinductance stage having a complex output impedance, and

ii. providing a control terminal circuit which controls gain of the second active device;

coupling an input of the second digital buffer to the output of the first digital buffer; and

coupling the output terminal of the first active load device to the control terminal circuit of the second active load device.

57. A method according to claim 56, wherein the digital buffers are current mode logic circuits.

58. A method according to claim 56, wherein each digital buffer includes a differential switch pair circuit having a pair of differential inputs and a pair of differential outputs.

59. A method according to claim 58, further comprising:

for each differential output of each active device, coupling an active device so as to form a differential load circuit.

60. A method according to claim 59, further comprising:

for each active device, coupling a gate impedance setting resistance between a device voltage source and a device control terminal.

61. A method according to claim 59, wherein the active devices are medium threshold voltage devices.

62. A method according to claim 61, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

63. A method according to claim 62, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

64. A method according to claim 59, wherein the active devices are low threshold voltage devices.

65. A method according to claim 64, wherein each active device includes a back gate which is isolated and biased to a potential near a device supply voltage.

66. A method according to claim 65, wherein a back gate supply diode coupled to the device supply voltage provides the potential for each back gate.

67. A method according to claim 59, further comprising:

for each buffer, coupling the differential outputs to each other with a trickle current arrangement to allow a trickle flow of current.

68. A method according to claim 59, further comprising:

for each differential output of each buffer, coupling a trickle current arrangement between the output and a device supply voltage to allow a trickle flow of current.

69. A method according to claim 59, further comprising:

for each differential output of each buffer, coupling a series damping resistance to the associated active load device.

70. A method according to claim 56, further comprising:

for each active load device, providing a load current path for a preceding circuit stage with an auxiliary drain current resistance.

71. A method according to claim 56, wherein the digital buffers are clock signal buffers.

72. A method according to claim 56, wherein the digital buffers are data signal buffers.

73. A crosspoint switch adapted to use a method for loading a high speed digital data circuit according to claim 56.