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High-speed differential logic buffer

  • US 20060061391A1
  • Filed: 09/20/2004
  • Published: 03/23/2006
  • Est. Priority Date: 09/20/2004
  • Status: Active Grant
First Claim
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1. A circuit for a high speed digital buffer, the circuit comprising:

  • an active load circuit connected to an output of a high speed digital buffer and loading the buffer output with an active transinductance stage having a complex output impedance.

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