Method and apparatus for receiving high speed signals with low latency

• US 20060061405A1
• Filed: 11/14/2005
• Published: 03/23/2006
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Jared L Zerbe
• Original Assignee: Jared L Zerbe
• Inventors: Zerbe, Jared L.
• Granted Patent: US 7,126,408 B2
• Time in Patent Office: Days
• US Class Current: 327/336
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00323 Delay compensation
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03M 5/20 the pulses having more than three levels
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/028 : Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 : Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03878 : Line equalisers; line build-out devices
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Claims

1. A multi-phased receiver system comprising:

a set of receivers coupled to the same input pin, each receiver receiving an input signal from the input pin, the input signal comprising a stream of input symbols, each input symbol having a symbol cycle time, the set of receivers configure to sequentially activated by a set of timing signals so as to receive respective input symbols during a sequence of symbol cycles, such that each receiver determines a logic signal representing a state of its respective input symbol during a respective symbol cycle of the sequence of symbol cycles in response to the timing signals, and the set of receivers outputs the logic signal representing the state of one of the input symbols during each bit cycle time.