SWITCHED-CAPACITOR CIRCUIT AND PIPELINED A/D CONVERTER

• US 20060061502A1
• Filed: 02/28/2005
• Published: 03/23/2006
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kudo, Masahiro, Yoshioka, Masato
• Granted Patent: US 7,030,804 B2
• Time in Patent Office: Days
• US Class Current: 341/172
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

An input capacitor and a plurality of reference capacitors sample an input voltage and reference voltages in a first period. A switch circuit connects the input capacitor and one of the reference capacitors between an output and an input of an amplifier in a second period. This mechanism causes a feedback gain to be “1” in the second period. Therefore, it is possible to reduce power consumption and noise.

Claims

1. A switched-capacitor circuit comprising:

an input capacitor and first to n^th reference capacitors (n is an integer equal to or larger than

     2) sampling an input voltage and first to n^th reference voltages, respectively, in a first period;

an amplifier generating an output voltage corresponding to the input voltage in a second period subsequent to the first period; and

a switch circuit that, in the second period, connects said input capacitor between an output and an input of said amplifier and connects at least one of said first to n^th reference capacitors between the output and the input of said amplifier according to a control signal.

2. The switched-capacitor circuit according to claim 1, wherein

said switch circuit includes:

an input switch that connects both ends of said input capacitor to a node of the input voltage and a node of a fixed voltage in the first period and to the input and the output of said amplifier in the second period; and

a reference switch that connects both ends of each of said reference capacitors to a node of each of the reference voltages and a node of the fixed voltage in the first period and to the input and the output of said amplifier according to the control signal in the second period.

3. The switched-capacitor circuit according to claim 1, wherein

said switch circuit includes:

an input switch that connects one end of said input capacitor to a node of the input voltage in the first period and to the output of said amplifier in the second period;

a reference switch that connects both ends of each of said reference capacitors to a node of each of the reference voltages and the input of said amplifier in the first period and to the input and the output of said amplifier according to the control signal in the second period; and

a short switch that shorts the output and the input of said amplifier to each other in the first period.

4. The switched-capacitor circuit according to claim 1, wherein:

said amplifier is a differential amplifier having complementary inputs and complementary outputs; and

said input capacitor and said reference capacitors are formed for each pair of the input and the output of said amplifier.

5. The switched-capacitor circuit according to claim 1, wherein:

each of said first to n^th reference capacitors is constituted of a plurality of sub-capacitors arranged in parallel; and

said switch circuit connects at least two of the sub-capacitors between the output and the input of said amplifier according to the control signal in the second period.

6. The switched-capacitor circuit according to claim 1, further comprising

a comparing circuit that compares magnitudes of the input voltage and a comparison voltage to output a comparison result as the control signal in a third period set between the first period and the second period.

7. The switched-capacitor circuit according to claim 6, wherein

said comparing circuit includes:

a comparison capacitor sampling the input voltage;

a comparator whose input is connected to one end of the comparison capacitor and which outputs the control signal from an output thereof; and

a comparing switch that connects both ends of the comparison capacitor to a node of the input voltage and a node of the fixed voltage in the first period and to a node of the comparison voltage and the input of the comparator in the third period.

8. A pipelined A/D converter comprising:

a plurality of stages connected in cascade, converting an analog voltage to a digital value in sequence from a higher-order digit, wherein;

at least one of said stages has a switched-capacitor circuit; and

the switched-capacitor circuit includes;

an input capacitor and first to n^th reference capacitors (n is an integer equal to or larger than

     2) sampling an input voltage and first to n^th reference voltages, respectively, in a first period;

an amplifier generating an output voltage corresponding to the input voltage in a second period subsequent to the first period; and

a switch circuit that, in the second period, connects said input capacitor between an output and an input of said amplifier and connects at least one of said first to n^th reference capacitors between the output and the input of said amplifier according to a control signal.

9. The pipelined A/D converter according to claim 8, further comprising

an encoding unit that encodes bit values respectively outputted from sub A/D converters formed in said stages, to output a digital value consisting of a plurality of bits.

10. The pipelined A/D converter according to claim 8, further comprising

a switch control circuit generating the control signal for turning on/off said switch circuit, wherein

each of said stages includes a sub A/D converter generating a bit value of the digital value;

and

said switch control circuit generates the control signal according to the bit value outputted by the sub A/D converter connected to an input of said switched-capacitor circuit.

11. The pipelined A/D converter according to claim 8, wherein

said switch circuit includes:

an input switch that connects both ends of said input capacitor to a node of the input voltage and a node of a fixed voltage in the first period and to the input and the output of said amplifier in the second period; and

a reference switch that connects both ends of each of said reference capacitors to a node of each of the reference voltages and a node of the fixed voltage in the first period and to the input and the output of said amplifier according to the control signal in the second period.

12. The pipelined A/D converter according to claim 8, wherein

said switch circuit includes:

an input switch that connects one end of said input capacitor to a node of the input voltage in the first period and to the output of said amplifier in the second period;

a reference switch that connects both ends of each of said reference capacitors to a node of each of the reference voltages and the input of said amplifier in the first period and to the input and the output of said amplifier according to the control signal in the second period; and

a short switch that shorts the output and the input of said amplifier to each other in the first period.

13. The pipelined A/D converter according to claim 8, wherein:

said amplifier is a differential amplifier having complementary inputs and complementary outputs; and

said input capacitor and said reference capacitors are formed for each pair of the input and the output of said amplifier.

14. The pipelined A/D converter according to claim 8, wherein:

each of said first to n^th reference capacitors is constituted of a plurality of sub-capacitors arranged in parallel; and

said switch circuit connects at least two of the sub-capacitors between the output and the input of said amplifier according to the control signal in the second period.

15. The pipelined A/D converter according to claim 8, further comprising

a comparing circuit that compares magnitudes of the input voltage and a comparison voltage to output a comparison result as the control signal in a third period set between the first period and the second period.

16. The pipelined A/D converter according to claim 15, wherein

said comparing circuit includes:

a comparison capacitor sampling the input voltage;

a comparator whose input is connected to one end of the comparison capacitor and which outputs the control signal from an output thereof; and

a comparing switch that connects both ends of the comparison capacitor to a node of the input voltage and a node of the fixed voltage in the first period and to a node of the comparison voltage and the input of the comparator in the third period.