Read-out circuit of image sensor

• US 20060061675A1
• Filed: 09/07/2005
• Published: 03/23/2006
• Est. Priority Date: 09/08/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Inventors: Kim, Nam-Ryeol
• Granted Patent: US 7,956,908 B2
• Time in Patent Office: Days
• US Class Current: 348/311
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A read-out circuit of an image sensor is provided. The read-out circuit includes: a CDS block, including: a plurality of reset capacitors storing inputted reset values of pixels; a plurality of signal capacitors storing inputted signal values of the pixels; a plurality of reset driving devices outputting the reset values stored into the reset capacitors; a plurality of signal driving devices outputting the signal values stored into the signal capacitors; and a plurality of capacitor equalization devices equalizing electric potential levels of the reset capacitors and the signal capacitors; a reset line transferring reset value output signals of the CDS block; a signal line transferring signal value output signals of the CDS block; a differential amplification unit amplifying a difference between the individual reset value output signal and the individual signal value output signal; and a line equalization device equalizing electric potential levels of the reset line and signal line.

Claims

1. A read-out circuit of an image sensor, comprising:

a correlated double sampling (CDS) block, including;

a plurality of reset capacitors storing inputted reset values of pixels;

a plurality of signal capacitors storing inputted signal values of the pixels;

a plurality of reset driving devices outputting the reset values stored into the reset capacitors;

a plurality of signal driving devices outputting the signal values stored into the signal capacitors; and

a plurality of capacitor equalization devices equalizing electric potential levels of the reset capacitors and the signal capacitors;

a reset line transferring reset value output signals of the CDS block;

a signal line transferring signal value output signals of the CDS block;

a differential amplification unit amplifying a difference between the individual reset value output signal and the individual signal value output signal; and

a line equalization device equalizing electric potential levels of the reset line and the signal line.

2. The read-out circuit of claim 1, wherein the CDS block further includes:

a plurality of reset input switches transferring the reset values of the pixels to the corresponding reset capacitors; and

a plurality of signal input switches transferring the signal values of the pixels to the corresponding signal capacitors.

3. The read-out circuit of claim 1, wherein the CDS block further includes:

a plurality of reset output switches transferring the reset value output signals to the reset line; and

a plurality of signal output switches transferring the signal value output signals to the signal line.

4. The read-out circuit of claim 1, wherein the plurality of reset driving devices and the plurality of signal driving devices are source followers each including two metal oxide semiconductor (MOS) transistors.

5. The read-out circuit of claim 1, wherein the differential amplification unit includes two input terminals and generates an output in proportion to a changed level of a voltage difference when the two input terminals have the changed voltage difference.

6. The read-out circuit of claim 5, wherein the differential amplification unit includes:

a differential amplifier including two input terminals and two output terminals;

two input capacitors making an individual connection with the two input terminals; and

two feedback capacitors each connected between the corresponding input terminal and the corresponding output terminal.

7. The read-out circuit of claim 1, wherein the capacitor equalization devices are MOS transistor switches.

8. The read-out circuit of claim 1, wherein the line equalization device is a MOS transistor switch.

9. The read-out circuit of claim 1, wherein the capacitor equalization devices and the line equalization device are turned on for the same period after the reset value output signals and the signal value output signals are transferred to the differential amplification unit.

10. The read-out circuit of claim 1, wherein:

the capacitor equalization devices and the line equalization device are simultaneously turned on after the reset value output signals and the signal value output signals are transferred to the differential amplification unit;

the line equalization device is turned off after a predetermined delay time; and

the capacitor equalization devices are tuned off after a predetermined delay time.

11. A read-out circuit of an image sensor, comprising:

a CDS block, including;

a plurality of reset capacitors receiving reset values of pixels and storing the reset values;

a plurality of signal capacitors receiving signal values of the pixels;

a plurality of reset driving devices outputting the reset values stored into the reset capacitors;

a plurality of signal driving devices outputting the signal values stored into the signal capacitors; and

a plurality of capacitor equalization devices equalizing electric potential levels of the reset capacitors and the signal capacitors;

a reset line transferring reset value output signals of the CDS block;

a signal line transferring signal value output signals of the CDS block; and

a differential amplification unit amplifying a difference between the individual reset value output signal and the individual signal value output signal.

12. The read-out circuit of claim 11, wherein the CDS block includes:

a plurality of reset input switches transferring the reset values of the pixels to the corresponding reset capacitors; and

a plurality of signal input switches transferring the signal values of the pixels to the corresponding signal capacitors.

13. The read-out circuit of claim 11, wherein the CDS block further includes:

a plurality of reset output switches transferring the reset value output signals to the reset line; and

a plurality of signal output switches transferring the signal value output signals to the signal line.

14. The read-out circuit of claim 11, wherein the plurality of reset driving devices and the plurality of signal driving devices are source followers each including two MOS transistors.

15. The read-out circuit of claim 11, wherein the differential amplification unit includes two input terminals and generates an output in proportion to a changed level of a voltage difference when the two input terminals have the changed voltage difference.

16. The read-out circuit of claim 15, wherein the differential amplification unit includes:

a differential amplifier including two input terminals and two output terminals;

two input capacitors making an individual connection with the two input terminals; and

two feedback capacitors each connected between the corresponding input terminal and the corresponding output terminal.

17. The read-out circuit of claim 11, wherein the capacitor equalization devices are MOS transistor switches.

18. The read-out circuit of claim 11, wherein the capacitor equalization devices equalize electric potential levels of the reset capacitors and the signal capacitors after the reset value output signals and the signal value output signals are transferred to the differential amplification unit.

19. A read-out circuit of an image sensor, comprising:

a CDS block storing and outputting reset values and signal values of pixels;

a reset line transferring reset value output signals of the CDS block;

a signal line transferring signal value output signals of the CDS block;

a differential amplification unit amplifying a difference between the individual reset value output signal and the individual signal value output signal; and

a line equalization device equalizing electric potential levels of the reset line and the signal line.

20. The read-out circuit of claim 19, wherein the differential amplification unit includes two input terminals and generates an output in proportion to a changed level of a voltage difference when the two input terminals have the changed voltage difference.

21. The read-out circuit of claim 20, wherein the differential amplification unit includes:

a differential amplifier including two input terminals and two output terminals;

two input capacitors making an individual connection with the two input terminals; and

two feedback capacitors each connected between the corresponding input terminal and the corresponding output terminal.

22. The read-out circuit of claim 19, wherein the CDS block includes:

a plurality of reset capacitors receiving the reset values of the pixels and storing the reset values;

a plurality of signal capacitors receiving the signal values of the pixels and storing the signal values;

a plurality of reset driving devices outputting the reset values stored into the reset capacitors; and

a plurality of signal driving devices outputting the signal values stored into the signal capacitors.

24. The read-out circuit of claim 22, wherein the CDS block further includes:

a plurality of reset output switches transferring the reset value output signals to the reset line; and

a plurality of signal output switches transferring the signal value output signals to the signal line.

25. The read-out circuit of claim 19, wherein the line equalization device is a MOS transistor switch.

26. The read-out circuit of claim 19, wherein the line equalization device equalizes the reset line and the signal line after the reset value output signals and the signal value output signals are transferred to the differential amplification unit.

23. The read-out circuit of 22, wherein the CDS block further includes:

a plurality of reset input switches transferring the reset values of the pixels to the corresponding reset capacitors; and

a plurality of signal input switches transferring the signal values of the pixels to the corresponding signal capacitors.