Flash memory data correction and scrub techniques

• US 20060062048A1
• Filed: 11/10/2005
• Published: 03/23/2006
• Est. Priority Date: 10/03/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Carlos J. Gonzalez, Kevin M. Conley
• Inventors: Conley, Kevin M., Gonzalez, Carlos J.
• Granted Patent: US 7,224,607 B2
• Time in Patent Office: Days
• US Class Current: 365/185.110
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

Claims

1. A non-volatile memory system, comprising:

an array of flash memory cells organized into blocks of a minimum number of memory cells that are erasable together and the blocks individually storing a plurality of units of data, and

a controller coupled with the memory cell array and that operates to;

identify when a scrub trigger event has occurred for data stored in at least one of the units of data in a first one of the blocks,

read the identified at least one unit of data from the first block,

correct any errors in the data read from the first block to provide corrected first block data,

write the corrected first block data as at least one unit of data to a second one of the blocks, and

thereafter copy uncorrected data units of the first block into the second block, thereby to consolidate in the second block corrected and uncorrected units of data originally of the first block.

2. The memory system claim 1, wherein the controller, prior to writing the corrected first block data into the second block, additionally operates to temporarily store the corrected first block data in a third block.

3. The memory system claim 2, wherein the controller additionally operates to:

identify when a disturbing event has occurred for at least one of the units of data stored in a fourth one of the blocks,

read the identified at least one unit of data from the fourth block,

correct any errors in the data read from the fourth block to provide corrected fourth block data,

temporarily store the corrected fourth block data in the third block,

thereafter write the corrected fourth block data as at least one unit of data to a fifth one of the block, and

thereafter copy uncorrected data units of the fourth block into the fifth block, thereby to consolidate in the fifth block corrected and uncorrected units of data originally of the fourth block.

4. The memory system claim 1, wherein the controller additionally operates to recognize the scrub trigger event to include an event disturbing said at least one of the data units stored in the first block.

5. The memory system claim 1, wherein the controller additionally operates to pause the operation after reading the data but before correcting any errors thereof, until other higher priority operations are performed.

6. The memory system claim 1, wherein the controller additionally operates to pause the operation after correcting any errors thereof but before writing the corrected data, until other higher priority operations are performed.

7. A non-volatile memory system, comprising:

an array of flash memory cells, and

a controller coupled with the memory cell array and that operates to;

identify when a scrub trigger event has occurred for data stored in at least one location of the array,

read the data stored in said at least one location in the array,

temporarily store information about said at least one location and the data read therefrom,

while this information remains stored, program or read other data to or from at least locations within the array other than said at least one location,

thereafter determine whether there are any errors in the data read from said at least one location in the array,

utilize the stored information to correct any errors in the data read from said at least one location in the array, and

write the corrected data into the array.

8. The memory system of claim 7, wherein the controller further operates to recognize an event disturbing data stored in said at least one location in the array as a scrub trigger event.

9. A non-volatile memory system, comprising:

an array of flash memory cells,

a controller coupled with the memory cell array and that operates to;

identify when a scrub trigger event has occurred for data stored in at least one location of the array,

read the data stored in said at least one location in the array,

thereafter determine whether there are any errors in the data read from said at least one location in the array,

correct any errors in the data read from said at least one location in the array,

temporarily store the corrected data,

while the corrected data remain temporarily stored, program or read other data to or from at least locations within the array other than said at least one location, and

thereafter writing the corrected data into the memory cell array.

10. The memory system of claim 9, wherein the controller further operates to recognize an event disturbing the data stored in said at least one location in the array as a scrub trigger event.

11. A memory system, comprising:

an array of erasable and re-programmable non-volatile memory cells organized into blocks of a minimum number of memory cells that are erasable together and that individually include a plurality of pages which individually store one or more units of data,

a controller coupled with the memory cell array and that operates to;

in response to the occurrence of at least one of a plurality of predefined events, identify at least one page of at least one block to be scrubbed,

read data stored in said at least one page with a first set of read conditions,

determine whether there are any errors in the read data, and, if so, whether the errors can be corrected,

in response to determining that the errors in the read data cannot be corrected, re-read the data stored in said at least one page with a second set of read conditions,

determine whether there are any errors in the re-read data, and, if so, whether the errors can be corrected,

in response to other memory activity being scheduled, deferr further action with respect to the read or re-read data,

after the other memory activity is completed and in response to determining that the errors in either of the read or re-read data can be corrected, correct such errors to provide corrected data, and

write the corrected data into at least a second page of a second block different from said one block.

12. The memory system of claim 11, wherein the controller additionally operates to copy unchanged data from pages within said at least one block into the second block.

13. A memory system, comprising:

a plurality of groups of re-programmable non-volatile memory cells that store data as levels of charge therein, wherein the groups individually store a plurality of units of data, and

a controller coupled with the memory cells and which operates as follows;

in response to the occurrence of at least one predefined condition, data are read from at least one unit of a first group of memory cells,

it is then determined whether there are any errors in the read data,

in response to at least errors being determined to exist in the read data, an effort is made to recover the data erroneously read from said at least one unit of the first group,

if recovered, the recovered data are written into at least one unit of a second group of memory cells different from the first group of memory cells, and

data read without errors from other units of the first group of memory cells are copied into units of the second group of memory cells other than its said at least one unit, thereby to consolidate in the second block data read without errors and recovered data originally of the first block.

14. The memory system of claim 13, wherein the controller further operates, before the recovered data are written into said at least one unit of the second group, to write the recovered data into a third group different from the first and second groups along with data recovered from at least one group other than the first, second or third groups, and thereafter copy the recovered data from the third group into the second group and copy data read without errors from other units of the first group into the second group.

15. The memory system of claim 13, wherein the controller further operates to recover the erroneously read data by using an error correction code read along with the data to recover the erroneously read data.

16. The memory system of claim 15, wherein the controller operates to recover the erroneously read data, if the use of the error correction code is not successful, by re-reading the data under different conditions than the data are initially read.

17. The memory system of claim 13, wherein the controller recognizes said at least one predefined condition to include any one or more of programming, reading or erasing memory cells having at least one conductor in common with at least some of the memory cells of said at least one unit of the first group of memory cells.

18. The memory system of claim 13, wherein the controller operates to recognize said at least one predefined condition to include receiving a command from a host to which the groups of memory cells are operably connected through the controller.

19. The memory system of claim 13, wherein the controller operates to recognize said at least one predefined condition to include storage of current data in said at least one unit of a first group of memory cells for fewer than a predefined number of memory operations.

20. The memory system of claim 13, wherein the controller operates to recognize said at least one predefined condition to include an identification of said at least one unit of the first group of memory cells by a deterministic or random sequence.

21. The memory system of claim 13, wherein the controller further operates to simultaneously erase the memory cells in individual ones of the groups.

22. The memory system of claim 13, wherein the controller further operates to simultaneously program the memory cells receiving individual ones of the units of data.

23. A memory system, comprising:

groups of re-programmable non-volatile memory cells that store data as levels of charge therein, wherein individual ones of the groups store a plurality of units of data, and

a controller coupled with the memory cells and which operates to;

read data from at least a first group of memory cells,

thereafter determine whether there are any errors in the data read from at least one unit of the first group of memory cells,

in response to at least errors being determined to exist in the read data, an effort is made to recover the data erroneously read from said at least one unit of the first group,

if recovered, the recovered data are written into at least one unit of a second group of memory cells different from the first group of memory cells, and

data read without errors from other units of the first group of memory cells are copied into units of the second group of memory cells other than its said at least one unit, thereby to consolidate in the second block data read without errors and recovered data originally of the first block.

24. The memory system of claim 23, wherein the controller further operates, before the recovered data are written into said at least one unit of the second group, to write the recovered data into a third group different from the first and second groups along with data recovered from at least one group other than the first, second or third groups, and thereafter copy the recovered data from the third group into the second group and copy data read without errors from other units of the first group into the second group.

25. The memory system of claim 23, wherein the controller further operates to include use of an error correction code read along with the data as part of the effort to recover the erroneously read data.

26. The memory system of claim 25, wherein the controller further operates, as part of the effort to recover the erroneously read data if the use of the error correction code is not successful, to re-read the data under different conditions than the data are initially read.

27. The memory system of claim 23, wherein the controller further operates to simultaneously erase the memory cells in individual ones of the groups.

28. The memory system of claim 23, wherein the controller further operates to simultaneously program the memory cells receiving individual ones of the units of data.