Fast-lock clock-data recovery system

• US 20060062341A1
• Filed: 12/17/2004
• Published: 03/23/2006
• Est. Priority Date: 09/20/2004
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Edmondson, John H., Farjad-rad, Ramin, Eble, John, Barakat, Shadi
• Application Number:
  US11/016,513
• Publication Number:
  US 20060062341A1
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A fast-locking clock-data recovery (CDR) system. The CDR system slews the phase of a sampling clock signal at a first slew rate in response to detecting an out-of-alignment condition between a first sampling clock signal and a data signal. Then, after exiting the out-of-alignment condition, the CDR system slews the phase of the sampling clock signal at a second, slower slew rate.

Claims

1. A method of operation within clock-data recovery (CDR) circuitry, the method comprising:

detecting an out-of-alignment condition between a first sampling clock signal and a data signal;

slewing the phase of the first sampling clock signal at a first slew rate in response to detecting the out-of-alignment condition; and

slewing the phase of the first sampling clock signal at a second, slower slew rate after exiting the out-of-alignment condition.

2. The method of claim 1 wherein detecting the out-of-alignment condition comprises detecting transitions of the data signal that occur within a predetermined time of a transition of the first sampling clock signal.

3. The method of claim 2 wherein each transition of the data signal that occurs within the predetermined time of a transition of the first sampling clock signal constitutes a large phase error event, and wherein detecting the out-of-alignment condition comprises detecting at least a first number of large phase error events within a first time interval.

4. The method of claim 3 wherein detecting at least the first number of large phase error events within the first time interval comprises incrementing and then decrementing a count value in response to each large phase error event.

5. The method of claim 4 wherein incrementing and then decrementing the count value comprises incrementing the count value at a first time and decrementing the count value at a second time, the second time occurring the first time interval after the first time.

6. The method of claim 4 wherein detecting at least the first number of large phase error events within the first time interval comprises comparing the count value with a threshold value.

7. The method of claim 6 further comprising storing the threshold value in a configuration circuit.

8. The method of claim 3 further comprising exiting the out-of-alignment condition upon detecting fewer than a second number of large phase error events within a second time interval.

9. The method of claim 8 wherein the second time interval is equal in duration to the first time interval.

10. The method of claim 8 wherein the second number of large phase errors is equal to the first number of large phase errors.

11. The method of claim 2 wherein detecting transitions of the data signal that occur within a predetermined time of a transition of the first sampling clock signal comprises sampling the data signal in response to the transition of the first sampling clock signal and in response to a transition of a second sampling clock signal, the second sampling clock signal being phase offset from the first sampling signal by a phase angle smaller than a phase angle between the first data sampling clock signal and an edge sampling clock signal.

12. The method of claim 11 wherein detecting transitions of the data signal that occur within a predetermined time of a transition of the first sampling clock signal further comprises comparing a first data sample generated by sampling the data signal in response to the first sampling clock signal to a second data sample generated by sampling the data signal in response to the second sampling clock signal.

13. The method of claim 12 wherein slewing the phase of the first sampling clock signal at a first slew rate comprises updating the phase of the first sampling clock signal in response to determining that the first data sample and second data sample do not match.

14. The method of claim 1 wherein slewing the phase of the first sampling clock signal at a first slew rate in response to detecting the out-of-alignment condition comprises updating the phase of the first sampling clock signal more frequently than at the second slew rate.

15. The method of claim 1 wherein slewing the phase of the first sampling clock signal at a first slew rate comprises adjusting the phase of the first sampling clock signal by a first phase angle in response to an update signal, and wherein slewing the phase of the first sampling clock signal at a second slew rate comprises adjusting the phase of the first sampling clock signal by a second phase angle in response to the update signal, the first phase angle having a greater magnitude than the second phase angle.

16. The method of claim 1 wherein slewing the phase of the sampling clock signal at a first slew rate in response to detecting the out-of-alignment condition comprises slewing the phase of the first sampling clock signal in a first slew direction in response to detecting the out-of-alignment condition, the method further comprising selecting the first slew direction based on a predominate slew direction of the first sampling clock signal prior to detecting the out-of-alignment condition.

17. An clock-data recovery (CDR) system comprising:

a clock generating circuit to generate a set of sampling clock signals;

a first phase update circuit to slew the phase of the sampling clock signals at a first slew rate in response to detecting an out-of-alignment condition between the sampling clock signals and a data signal; and

a second phase update circuit to slew the phase of the sampling clock signals at a second, slower slew rate after exiting the out-of-alignment condition.

18. The CDR system of claim 17 wherein the out-of-alignment condition is a metastable condition.

19. The CDR system of claim 17 wherein the clock generating circuit comprises:

a clock generator to generate a set of reference phase vectors;

an interpolator circuit to generate at least one of the sampling clock signals by interpolating between a pair of the reference phase vectors in accordance with a phase count value.

20. The CDR system of claim 19 wherein the clock generating circuit further comprises a phase counter to output the phase count value to the interpolator circuit, the phase counter being configured to adjust the phase count value in response count-adjust signals from the first phase update circuit and in response to count-adjust signals from the second phase update circuit.

21. The CDR system of claim 20 further comprising an arbiter circuit coupled between the phase counter and the first and second phase update circuits to selectively pass count-adjust signals to the phase counter from either the first phase update circuit or the second phase update circuit according to a predetermined prioritizing policy.

22. The CDR system of claim 17 further comprising a phase detection circuit to detect large phase error events and to output indications of the large phase error events to the first phase update circuit.

23. The CDR system of claim 17 further comprising a sampling circuit to generate multiple samples of each data eye in the data signal, the multiple samples including:

an edge sample captured in response to an edge clock signal of the sampling clock signals;

a first data sample captured in response to a data clock signal of the sampling clock signals; and

first and second near-data samples captured in response to a first and second near-data clock signals, respectively, of the sampling clock signals.

24. The CDR system of claim 23 further comprising a phase detection circuit to compare the first data sample with the first near-data sample to determine if a transition in the data signal occurred between a transition of the data clock signal and a transition of the first near-data clock signal.

25. The CDR system of claim 24 wherein the phase detection circuit is configured to signal a first type of large phase error event to the first phase update circuit in response to determining that a transition in the data signal occurred between the transition of the data clock signal and the transition of the first near-data clock signal.

26. The CDR system of claim 25 wherein the phase detection circuit is configured to signal a second type of large phase error event to the first phase update circuit in response to determining that a transition in the data signal occurred between a transition of the data clock signal and a transition of the second near-data clock signal.

27. The CDR system of claim 26 wherein the first phase update circuit comprises a trigger circuit to signal detection of the out-of-alignment condition in response to receiving signals from the phase detection circuit indicating that a threshold number of the first type of large phase error and a threshold number of the second type of large phase error have occurred within a first time interval.

28. The CDR system of claim 23 wherein the first phase update circuit comprises a trigger circuit to determine i) whether the first near-data sample differs from the first data sample at or above a first threshold rate and ii) whether the second near-data sample differs from the first data sample at or above a second threshold rate.

29. The CDR system of claim 28 wherein the first threshold rate and the second threshold rate are the same threshold rate.

30. The CDR system of claim 28 wherein the trigger circuit is configured to signal detection of the out-of-alignment condition if the first near-data sample differs from the first data sample at or above the first threshold rate and the second near-data sample differs from the first data sample at or above the second threshold rate.

31. The CDR system of claim 17 wherein, upon detecting the out-of-alignment condition, the first phase update circuit is configured to slew the phase of the sampling clock signals in a first slew direction in response to phase error indications that indicate a phase update in the first slew direction, and is further configured to refrain from slewing the phase of the sampling clock signals in a direction opposite the first slew direction in response to phase error indications that indicate a phase update in the direction opposite the first slew direction.

32. The CDR system of claim 17 wherein the first phase update circuit comprises a sustain logic circuit to sustain phase updates in a selected slew direction for a period of time after events that indicate phase updates in the selected slew direction cease.

33. An apparatus comprising:

means for detecting an out-of-alignment condition between a first sampling clock signal and a data signal;

means for slewing the phase of the first sampling clock signal at a first slew rate in response to detecting the out-of alignment condition; and

means for slewing the phase of the first sampling clock signal at a second, slower slew rate after exiting the out-of-alignment condition.

34. Computer-readable media having information embodied therein that includes a description of a clock-data recovery (CDR) system, the information including descriptions of:

a clock generating circuit to generate a set of sampling clock signals;

a first phase update circuit to slew the phase of the sampling clock signals at a first slew rate in response to detecting an out-of-alignment condition between the sampling clock signals and a data signal; and

a second phase update circuit to slew the phase of the sampling clock signals at a second, slower slew rate after exiting the out-of-alignment condition.