Test structure and method for yield improvement of double poly bipolar device

• US 20060063282A1
• Filed: 09/22/2004
• Published: 03/23/2006
• Est. Priority Date: 09/22/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Kerr, Daniel Charles, Esry, Thomas Craig, Martin, Edward Paul Jr., Albers, Bradley J., Patterson, Oliver Desmond
• Granted Patent: US 7,074,628 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: G01R 31/2648 Characterising semiconductor materials testing of materials or semi-finished products G01R31/2831; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

Claims

1. A method of detecting crystal lattice defects in semiconductor manufacturing wherein a plurality of double-poly NPN transistors are formed in each of a plurality of spaced dies on a semiconductor wafer having a P-type substrate, comprising:

forming a test circuit on the wafer, the test circuit comprising a plurality of semiconductor structures having an N-type emitter structure overlaying a P-type base structure overlaying P-type material integrated with the wafer substrate;

charging the test circuit with an electron beam;

detecting secondary electrons emitted from the N-type emitter of the transistor structures; and

identifying test circuits exhibiting crystal lattice detects as a function of secondary electron emission.

2. The method of claim 1 and including crystal structure analysis of identified devices to determine manufacturing process adjustments.

3. The method of claim 1 wherein the semiconductor structures are formed concurrently with formation of transistors in the dies.

4. The method of claim 1 wherein the steps of charging, detecting and identifying comprise passive voltage contrast measurement.

5. The method of claim 1 wherein the test circuits are located in spaces between dies.

6. The method of claim 1 wherein the step of identifying comprises identifying circuits having a bright appearance indicative of significant secondary electron emission.

7. A system for detecting crystal lattice defects in NPN bipolar transistor structures formed on a wafer having a substrate of P-type material, comprising:

a plurality of test circuits formed on the wafer, each test circuit comprising a first N-type material layer over a second P-type material layer, the first and second layers having structural characteristics of an NPN transistor emitter and base, respectively;

a P-type material under the second layer and continuing into the substrate of the wafer; and

a PVC system arranged to examine the test circuits and for providing data indicative of electron leakage from the wafer substrate to the first N-type material layer caused by defects at the NP junction between the first and second layers.