Memory cell and method for forming the same
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Accused Products
Abstract
A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.
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Citations
100 Claims
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1-75. -75. (canceled)
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76. A method for forming a plurality of memory cells structures on a surface of a substrate, comprising:
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forming an active region in the substrate;
forming a plurality of posts on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
forming a plurality of contacts over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
forming a plurality of memory cell capacitors on a respective one of the plurality of posts; and
forming a plurality of gate structures adjacent a respective one of the plurality of posts to form a respective vertical transistor to electrically couple the respective memory cell capacitor to the active region. - View Dependent Claims (78, 79, 80, 81, 82, 83, 84)
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77. The method of 76 wherein forming the plurality of contacts comprises forming each contact of the plurality of contacts over a respective portion of the active region that extends laterally on the surface of the substrate from a respective region between a pair of posts.
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85. A method for forming a plurality of memory cells structures on a surface of a substrate, comprising:
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forming an active region in the substrate;
forming a semiconductor post on the active region;
forming first and second contacts on the active region and laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;
forming a memory cell capacitor on the semiconductor post; and
forming a vertical access transistor having a gate adjacent the semiconductor post and to electrically couple the capacitor to the first and second contacts in response to being activated. - View Dependent Claims (86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100)
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Specification