U-GATE TRANSISTORS AND METHODS OF FABRICATION

• US 20060063332A1
• Filed: 09/23/2004
• Published: 03/23/2006
• Est. Priority Date: 09/23/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert, Doyle, Brian, Brask, Justin, Singh, Surinder Pal
• Granted Patent: US 7,071,064 B2
• Time in Patent Office: Days
• US Class Current: 438/267
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A process is described for manufacturing of non-planar multi-corner transistor structures. A fin of a semiconductor material having a mask on a top surface of the fin is formed on a first insulating layer. A second insulating layer is formed on the fin exposing a top surface of the mask, wherein a protection layer is deposited between the fin and the second insulating layer. Next, the mask is removed and spacers are formed on the fin adjacent to the protection layer. A recess having a bottom and opposing sidewalls is formed in the fin. A gate dielectric layer and a gate electrode are formed on the top surface, the opposing sidewalls of the fin and on the bottom and on the opposing sidewalls of the recess in the fin. A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a fin of a semiconductor material on a first insulating layer, wherein a mask layer is on a top surface of the fin;

forming a second insulating layer on the fin leaving a top surface of the mask layer exposed, wherein a protection layer is deposited between the fin and the second insulating layer;

removing the mask layer;

forming spacers on the top surface of the fin adjacent to the protection layer; and

forming a recess in the fin, the recess having a bottom and opposing sidewalls.

2. The method of claim 1, wherein a buffer layer is between a top surface of the fin and the mask layer.

3. The method of claim 2, wherein the protection layer covers two opposing sidewalls of the fin, two opposing sidewalls of the mask layer, and portions of the first insulating layer on opposite sides of the fin.

4. The method of claim 3, wherein the protection layer protects the two opposing sidewalls of the fin and the portions of the first insulating layer on opposing sides of the fin from being undercut.

5. The method of claim 3, wherein forming the second insulating layer on the fin

includes planarizing the second insulating layer such that a top surface of the second insulating layer is substantially planar with the top surface of the mask layer.

6. The method of claim 1, wherein forming the fin of the semiconductor material comprises

depositing a layer of the semiconductor material on the first insulating layer on the substrate;

depositing the mask layer on the layer of the semiconductor material;

patterning and etching the mask layer on the layer of the semiconductor material; and

etching the layer of the semiconductor material to form the fin.

7. The method of claim 1, further comprising:

forming a gate dielectric layer covering the top surface and the opposing sidewalls of the fin and the bottom and the opposing sidewalls of the recess in the fin;

forming a gate electrode on the gate dielectric layer; and

forming a source region and a drain region in the fin at opposite sides of the gate electrode.

8. The method of claim 1, wherein the protection layer provides control over a thickness of the opposing sidewalls and the bottom of the recess.

9. The method of claim 1, wherein an etching rate of the protection layer is substantially lower than the etching rate of the mask layer.

10. The method of claim 9, wherein the protection layer includes carbon doped silicon nitride.

11. The method of claim 1, wherein a thickness of the mask layer determines a minimal thickness of the bottom of the recess.

12. The method of claim 1, wherein a width of each of the spacers determines a thickness of each of the opposing sidewalls of the recess.

13. The method of claim 1, wherein the bottom of the recess is thinner than each of the opposing sidewalls of the recess.

14. The method of claim 2, further comprising:

removing the spacers;

removing the buffer layer; and

removing the second insulating layer, after forming the recess in the fin.

15. A method of forming a semiconductor transistor structure comprising:

forming a fin of a semiconductor material on a first insulating layer on a substrate, the fin having a top surface, a first sidewall, and a second sidewall;

forming a recess in the fin, the recess having a bottom and sidewalls, wherein each of the sidewalls includes at least one step;

forming a gate dielectric layer on the top surface of the fin, on the first and the second sidewalls of the fin, on the bottom of the recess and on the sidewalls of the recess;

forming a gate electrode on the dielectric layer; and

forming a drain region and a source region at opposite sides of the gate electrode.

16. The method of claim 15, wherein forming a fin of a semiconductor material comprises

depositing a layer of the semiconductor material on the first insulating layer on the substrate;

depositing a hard mask layer on the layer of the semiconductor material, wherein a buffer layer is between the layer of the semiconductor material and the hard mask layer; and

patterning the hard mask layer to form the fin of the semiconductor material with the buffer layer between the top surface of the fin and the hard mask layer.

17. The method of claim 15, wherein forming the recess in the fin comprises

forming a protection layer on the hard mask layer, wherein the protection layer covers the first sidewall and the second sidewall of the fin, sidewalls of the hard mask layer, and portions of the first insulating layer at opposite sides of the fin;

forming a second insulating layer on the protection layer leaving the top surface of the hard mask layer exposed, wherein a top surface of the second insulating layer is substantially planar with a top surface of the hard mask layer;

removing the hard mask layer to expose the buffer layer;

forming spacers on the buffer layer adjacent to the protection layer; and

etching the fin from an exposed portion of the top surface of the fin down to a predetermined thickness.

18. The method of claim 17, wherein forming the second insulating layer on the protection layer comprises

depositing the second insulating layer on the protection layer;

and

polishing the second insulating layer back to expose the top surface of the hard mask layer.

19. The method of claim 17, wherein a ratio between a height of the spacers and a thickness of the fin defines a thickness of the bottom of the recess.

20. The method of claim 15, wherein the bottom of the recess and the sidewalls of the recess are thin enough to form a fully depleted channel.

21. The method of claim 15, wherein forming the recess in the fin further comprises

a. depositing a passivation layer on the bottom of the recess;

b. shrinking the spacers in size to expose portions of the top surface of the fin covered by the buffer layer;

c. etching away the exposed portions of the top surface of the fin covered by the buffer layer to form the step.

22. The method of claim 21, wherein operations a to c are continuously repeated until a predetermined amount of steps in the sidewalls of the recess is produced.

23. The method of claim 21, wherein a height of the step is equal to a width of the step.

24. A method of forming a semiconductor structure, comprising:

forming a fin of a semiconductor material on a first insulating layer, wherein a buffer layer is deposited between a top surface of the fin and a hard mask layer;

forming a second insulating layer on the fin leaving a top surface of the hard mask layer exposed, wherein a top surface of the second insulating layer is substantially planar with the top surface of the hard mask layer;

removing the hard mask layer to expose the buffer layer;

forming spacers on the buffer layer adjacent to the second insulating layer; and

etching the fin from the exposed portion of the top surface down to the first insulating layer to produce two halved fins.

25. The method of claim 24, wherein each of the two halved fins has sublithographic dimensions.

26. The method of claim 25, wherein a distance between the two halved fins is defined by a thickness of each of the spacers.

27. The method of claim 24, further comprising:

forming a gate dielectric layer covering the top surface and the two opposing sidewalls of each of the two fins;

forming a gate electrode on the gate dielectric layer; and

forming a source region and a drain region in each of the two fins at opposite sides of the gate electrode.

28. The method of claim 24 further comprising

forming a protection layer on the hard mask layer covering two opposing sidewalls of the fin, two opposing sidewalls of the hard mask layer, and portions of the first insulating layer on opposite sides of the fin.

29. The method of claim 24, wherein each of the two halved fins has a sidewall, which includes at least one step.

30. A method comprising:

forming a fin of a semiconductor material on a first insulating layer;

forming a second insulating layer on the fin leaving a top surface of the hard mask layer exposed, wherein a top surface of the second insulating layer is substantially planar with the top surface of the hard mask layer;

removing the hard mask layer to expose the buffer layer;

forming spacers on the buffer layer adjacent to a protection layer adjacent to the second insulating layer; and

etching the fin from the exposed portion of the top surface down to a predetermined depth;

depositing a passivation layer on the bottom of the recess;

shrinking the spacers in size to expose portions of the top surface of the fin covered by the buffer layer;

etching away the exposed portions of the top surface of the fin covered by the buffer layer to form the step.

31. The method of claim 30, wherein depositing a passivation layer, shrinking the spacers in size, and etching away the exposed portions of the top surface of the fin covered by the buffer layer are continuously repeated until a predetermined amount of steps in the sidewalls of the recess is produced.

32. The method of claim 30, wherein shrinking the spacers in size includes any one of dry etching and wet etching.

33. A semiconductor structure, comprising:

a fin of a semiconductor material on an insulating layer, the fin having a top surface, a first sidewall, a second sidewall, and first set of corners;

a recess in the fin, the recess having a bottom, a third sidewall, a forth sidewall, wherein the third sidewall and the forth sidewall are internal sidewalls of the recess, and second set of corners, wherein a number of the second set of corners are larger than the number of the first set of corners.

34. The semiconductor transistor structure of claim 33 further comprising:

a gate dielectric on the top surface of the fin, on the first sidewall, the second sidewall, and on the first set of corners of the fin and on the bottom of the recess, on the third sidewall, on the forth sidewall, and on the second set of corners of the recess in the fin;

a gate electrode formed on the gate dielectric; and

a source region and a drain region formed on opposite sides of the gate electrode.

35. The semiconductor transistor structure of claim 33, wherein the bottom of the recess, the third sidewall and the fourth sidewall of the recess are thin enough to form a fully depleted channel.

36. The semiconductor transistor structure of claim 33, wherein the first set of corners and second set of corners include right corners.

37. The semiconductor transistor structure of claim 33, wherein each of the sidewalls of the recess in the fin includes at least one step.