Integrated barrier and seed layer for copper interconnect technology

• US 20060063375A1
• Filed: 09/20/2004
• Published: 03/23/2006
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Burke, Peter A., Sun, Sey-Shing, Kwak, Byung-Sung L.
• Granted Patent: US 7,300,869 B2
• Time in Patent Office: Days
• US Class Current: 438/629
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated barrier and seed layer that is useful for creating conductive pathways in semiconductor devices. The barrier portion of the integrated layer prevents diffusion of the conductive material into the underlying dielectric substrate while the seed portion provides an appropriate foundation upon which to deposit the conductive material. The barrier portion of the integrated layer is formed of a metal nitride, while the seed portion is formed of ruthenium or a ruthenium alloy. The metal nitride forms an effective barrier layer while the ruthenium or ruthenium alloy forms an effective seed layer for a metal such as copper. In some embodiments, the integrated layer is formed in a way so that its composition changes gradually from one region to the next.

Claims

1. A method for fabricating an integrated barrier and seed layer comprising:

providing a dielectric layer having a plurality of recessed vias and trenches;

depositing a metal nitride over a surface of each of the vias and trenches to form a barrier layer; and

depositing a ruthenium or a ruthenium alloy over the barrier layer to form a seed layer.

2. A method as recited in claim 1 wherein the metal nitride that forms the barrier layer is a ruthenium-tantalum-nitride.

3. A method as recited in claim 2 wherein the seed layer is formed of a ruthenium-tantalum alloy.

4. A method as recited in claim 3 wherein the barrier and seed layer are deposited using a physical vapor deposition, a chemical vapor deposition, or an atomic layer deposition technique.

5. A method as recited in claim 3 further comprising:

gradually reducing the amount of nitrogen during the deposition of the metal nitride of the barrier layer such that a transitional layer is formed between the barrier layer and the seed layer and wherein the transitional layer gradually transitions from a metal nitride in the region adjacent to the barrier layer to a ruthenium or ruthenium alloy in the region adjacent to the seed layer.

6. A method as recited in claim 5 wherein the amount of nitrogen is gradually reduced by gradually turning off a supply of nitrogen gas into the deposition chamber.

7. A method as recited in claim 3 further comprising:

depositing copper onto the seed layer such that copper fills at least some of the vias and trenches, wherein the copper forms electrically conductive pathways within each copper filled via and trench.

8. A method as recited in claim 7 further comprising:

backpolishing the copper deposited onto the seed layer to form a substantially smooth surface on top of the dielectric layer.

9. A method as recited in claim 1 wherein the operation of depositing the barrier layer forms a barrier layer having a thickness in the range of approximately 1-10 nm.

10. A method as recited in claim 1 wherein the operation of depositing the seed layer forms a seed layer having a thickness in the range of approximately 1-10 nm.

11. A method as recited in claim 1 wherein the operations of depositing the barrier layer and the seed layer are performed with a single deposition tool.

12. A method as recited in claim 1 wherein the metal nitride that forms the barrier layer is a tantalum-nitride and wherein the copper seed layer is formed of substantially pure ruthenium.

13. A method as recited in claim 12 further comprising:

forming a transition layer formed of a ruthenium-tantalum-nitride between the barrier layer and the copper seed layer by depositing a ruthenium-tantalum-nitride after the operation of depositing the barrier layer and before the operation of depositing the copper seed layer.

14. A method as recited in claim 13 wherein the barrier and seed layer are deposited using an atomic layer deposition, physical vapor deposition, or a chemical vapor deposition technique.

15. A method as recited in claim 13 further comprising:

near the end of the operation of depositing the tantalum-nitride of the barrier layer, introducing and gradually increasing the amount of ruthenium being deposited such that the material composition of a top region of the barrier layer that is adjacent to the transition layer gradually increases in ruthenium content.

16. A method as recited in claim 15 further comprising:

near the end of the operation of depositing the ruthenium-tantalum-nitride of the transition layer, gradually decreasing the amount of tantalum and nitrogen being deposited such that the material composition of a top region of the transition layer that is adjacent to the seed layer gradually decreases in tantalum and nitrogen content.

17. A method as recited in claim 13 further comprising:

depositing copper onto the seed layer such that copper fills at least some of the vias and trenches, wherein the copper forms electrically conductive pathways within each copper filled via and trench.

18. A method as recited in claim 17 further comprising:

backpolishing the copper deposited onto the seed layer to form a substantially smooth surface on top of the dielectric layer.

19. A method as recited in claim 1 wherein the copper seed layer is formed of substantially pure ruthenium.

20. A method as recited in claim 1 wherein the dielectric layer is formed upon a semiconductor wafer substrate.

21. A semiconductor device comprising:

a semiconductor substrate that contains integrated circuits;

a dielectric layer formed above the semiconductor substrate, the dielectric layer having a plurality of recessed vias and trenches;

an integrated barrier and seed layer that covers a surface of each of the vias and trenches, the integrated barrier and seed layer having a barrier region that is formed adjacent to the surface of the dielectric layer and a seed region that is formed above the barrier region, the barrier region being formed of a metal nitride and the seed region being formed of ruthenium or a ruthenium alloy.

22. A semiconductor device as recited in claim 21 wherein the composition of integrated barrier and seed layer gradually transitions from the metal nitride of the barrier region to the ruthenium or ruthenium alloy of the seed region.

23. A semiconductor device as recited in claim 21 wherein the barrier region and the seed region of the integrated barrier and seed layer are each approximately 1-10 nm in thickness, respectively.

24. A semiconductor device as recited in claim 22 wherein the integrated barrier and seed layer further comprises:

a transition region between the barrier region and the seed region, the metal nitride of the barrier region being formed of at least a first metal and nitrogen and the transition region being formed of at least the first metal, nitrogen, and ruthenium.

25. A semiconductor device as recited in claim 24 wherein a bottom layer of the transition region gradually transitions in composition from the metal nitride of the barrier region to the composition of the first metal, nitrogen, and ruthenium of the transition region.

26. A semiconductor device as recited in claim 25 wherein a top layer of the transition region gradually transitions in composition from the first metal, nitrogen, and ruthenium of the transition region to the ruthenium or ruthenium alloy of the seed region.

27. A semiconductor device as recited in claim 21 further comprising:

copper metallization formed upon the integrated barrier and seed layer such that copper fills at least some of the vias and trenches, wherein the copper forms electrically conductive pathways.

28. A semiconductor device comprising:

a semiconductor substrate that contains integrated circuits;

a dielectric layer formed above the semiconductor substrate, the dielectric layer having a plurality of recessed vias and trenches; and

an integrated barrier and seed layer that covers a surface of each of the vias and trenches, the integrated barrier and seed layer having a barrier region that is formed adjacent to the surface of the dielectric layer and a seed region that is formed above the barrier region, the barrier region being formed of a ruthenium-tantalum-nitride and the seed region being formed of a ruthenium-tantalum alloy.

29. A semiconductor device as recited in claim 28 wherein the composition of integrated barrier and seed layer gradually transitions in composition from the ruthenium-tantalum-nitride of the barrier region to the ruthenium-tantalum alloy of the seed region.

30. A semiconductor device comprising:

a semiconductor substrate that contains integrated circuits;

a dielectric layer formed above the semiconductor substrate, the dielectric layer having a plurality of recessed vias and trenches; and

an integrated barrier and seed layer that covers a surface of each of the vias and trenches, the integrated barrier and seed layer having a barrier region that is formed adjacent to the surface of the dielectric layer, a transition region formed above the barrier region, and a seed region formed above the transition region, the barrier region being formed of a tantalum-nitride, the transition region formed of a ruthenium-tantalum-nitride, and the seed region being formed of substantially pure ruthenium.

31. A semiconductor device as recited in claim 30 wherein a bottom layer of the transition region gradually changes in composition from tantalum-nitride to ruthenium-tantalum-nitride.

32. A semiconductor device as recited in claim 31 wherein a top layer of the transition region gradually changes in composition from ruthenium-tantalum-nitride to substantially pure ruthenium.

33. A method for fabricating an integrated barrier and seed layer comprising:

providing a dielectric layer having a plurality of recessed vias and trenches;

forming an integrated barrier and seed layer over at least each of the vias and trenches by,

first, depositing a metal nitride to form a barrier region, and

second, depositing a ruthenium or a ruthenium alloy over the barrier region to form a seed region, wherein the first and second depositing operations are performed in a single deposition chamber.

34. A method as recited in claim 33 wherein the barrier region is formed of ruthenium-tantalum-nitride and wherein the seed region is formed of a ruthenium-tantalum alloy.

35. A method as recited in claim 33 wherein the barrier region is formed of tantalum-nitride and wherein the seed region is formed of substantially pure ruthenium.