Semiconductor-insulator-semiconductor structure for high speed applications

• US 20060063679A1
• Filed: 09/13/2005
• Published: 03/23/2006
• Est. Priority Date: 09/17/2004
• Status: Abandoned Application

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Yue, Cheisan J., Keyser, Thomas
• Application Number:
  US11/224,808
• Publication Number:
  US 20060063679A1
• Time in Patent Office: Days
• US Class Current: 505/190
• CPC Class Codes: G02F 1/025 in an optical waveguide structure G02F1/017, G02F1/2257 take precedence

Abstract

A semiconductor-insulator-semiconductor (SIS) device is presented along with a device for fabricating the same. The SIS device includes a lower semiconductor layer, an upper semiconductor layer, and a central insulating layer located between the overlapping portions of the lower semiconductor layer and the upper semiconductor layer. The central insulating layer is nitridized in order to make the layer less permeable to dopant species and to therefore minimize dopant cross-diffusion. Subsequently the switching characteristics of the SIS device are optimized when the SIS device is used as, for example, an integrated optical modulator.

Claims

1. A semiconductor-insulator-semiconductor device comprising:

a lower semiconductor layer laterally bounded by lateral isolation regions;

an upper semiconductor layer, having a first portion that at least partially overlaps the lower semiconductor layer and a second portion that at least partially overlaps a lateral isolation region; and

a central dielectric region located between the lower semiconductor layer and the first portion of the upper semiconductor layer, wherein the central dielectric region is nitridized.

2. The device of claim 1 wherein the bottom semiconductor layer comprises an active silicon layer of a silicon-on-insulator (SOI) substrate.

3. The device of claim 2 wherein the lower semiconductor layer is formed by:

creating a pattern mask on top of the active layer of the SOI substrate; and

etching the portions of the active layer not covered by the pattern mask to define the lower semiconductor layer.

4. The device of claim 3 wherein etching the portions of the active layer is accomplished using a dry etch process that utilizes fluorine or chlorine as an etchant.

5. The device of claim 1 wherein the upper semiconductor layer is poly-silicon grown using a chemical vapor deposition process.

6. The device of claim 1 wherein the lower semiconductor region is p-type and the upper semiconductor region is n-type.

7. The device of claim 1 wherein the central dielectric region is grown using a thermal growth process, and wherein the central dielectric region is nitridized by exposing the device to a nitrogen-containing source during the thermal growth process.

8. The device of claim 1 wherein the central dielectric region is grown using a thermal growth process, and wherein the central dielectric region is nitridized by exposing the device to a nitrogen-containing source after the thermal growth process.

9. The device of claim 1 wherein the central dielectric region is formed using a deposition process, and wherein the central dielectric region is nitridized by exposing the device to a a nitrogen-containing source during the deposition process.

10. The device of claim 1 wherein the central dielectric region is nitridized using a nitrogen implantation process.

11. The device of claim 1 wherein the central dielectric region has a nitrogen concentration between about 1 atomic percent to about 10 atomic percent.

12. The device of claim 1 wherein the central dielectric region has a thickness between about 10 Angstroms to about 80 Angstroms.

13. A method for creating a semiconductor-insulator-semiconductor device comprising:

providing an active semiconductor layer on an insulating substrate;

etching portions of the active semiconductor layer to create a laterally isolated lower semiconductor layer;

forming lateral isolation regions that laterally bound the lower semiconductor layer;

forming a central dielectric region over a first portion of the lower semiconductor layer, wherein the central dielectric region is nitridized; and

forming an upper semiconductor layer that at least overlaps the lower semiconductor layer, such that the central dielectric region forms the interface between the upper semiconductor layer and the lower semiconductor layer.

14. The method of claim 13 wherein forming the central dielectric region comprises:

thermally growing silicon dioxide in an atmosphere having controlled amounts of nitrogen, such that the silicon dioxide is nitridized; and

patterning the silicon dioxide by selectively etching portions of the silicon dioxide to define the central dielectric region.

15. The method of claim 13 wherein forming the central dielectric region comprises:

depositing a layer of silicon dioxide in a deposition chamber, wherein a controlled flow rate of nitrogen-containing gas is used in the deposition chamber such that the silicon dioxide is nitridized; and

patterning the silicon dioxide by selectively etching portions of the silicon dioxide to define the central dielectric region.

16. The method of claim 13 wherein the central dielectric region has a thickness between about 10 Angstroms to about 80 Angstroms.

17. The method of claim 13 wherein the central isolating region is nitridized by a nitrogen implantation process.

18. The method of claim 13 wherein the central dielectric region has a nitrogen concentration of about 1 atomic percent to about 10 atomic percent.

19. The method of claim 13 wherein the active semiconductor layer is the active silicon layer of a silicon-on-insulator (SOI) substrate.

20. The method of claim 13 wherein forming the upper semiconductor layer comprises:

depositing a layer of poly-silicon using a chemical vapor deposition (CVD) process; and

patterning the layer of poly-silicon by selectively etching portions of the poly-silicon to define the upper semiconductor layer.

21. The method of claim 20 further comprising performing a high-temperature annealing step to reduce the grain boundaries of the upper semiconductor layer.