Testing a data communication architecture

• US 20060064480A1
• Filed: 09/07/2004
• Published: 03/23/2006
• Est. Priority Date: 09/07/2004
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Lesartre, Gregg Bernard, Johnson, Tyler, Warner, Craig William
• Granted Patent: US 8,370,478 B2
• Time in Patent Office: Days
• US Class Current: 709/224
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A method, system, and apparatus for testing a scalable computer system is provided. In an illustrative implementation, a system for testing a scalable computer system includes configuring a single cell on a partitionable system to create an isolated test channel. A test packet is generated and provided to the test channel. The test channel inserts the test packet into the scalable computer system via a communications link, and a response to the insertion of the test packet is monitored to determine system performance.

Claims

1. A method of testing a data communication architecture comprising:

configuring a single cell test partition;

providing a test packet of at least one bit to said partition;

inserting said packet into said architecture via a communications link; and

monitoring a response to said inserting step.

2. The method as set forth in claim 1, wherein configuring a single cell test partition comprises establishing said single cell partition from an unused block.

3. The method as set forth in claim 2, wherein inserting said packet into said architecture further comprises initializing a link between said partition and a destination location for said packet.

4. The method as set forth in claim 2, wherein inserting said packet into said architecture comprises:

writing said at least one bit into a buffer; and

sending the contents of said buffer to said destination.

5. The method as set forth in claim 1 wherein said packet is representative of a hardware component.

6. The method as set forth in claim 5, wherein said packet is representative of a malfunctioning hardware component.

7. The method as set forth in claim 5, wherein said hardware component does not exist on system.

8. The method as set forth in claim 1, wherein said packet is software generated.

9. The method as set forth in claim 1, wherein the monitoring step includes generation of an error report.

10. A data communication architecture comprising:

a single cell partition capable of injecting a test packet into said network.

11. The architecture as set forth in claim 10 wherein said partition further comprises a buffer for storing a test packet.

12. A system for testing a data communication architecture comprising:

a scalable computer network; and

a single cell partition within said network configured to inject a test packet into said network.

13. A system as set forth in claim 12, further comprising a buffer to store said test packet.

14. A system as set forth in claim 12, wherein said packet is representative of bad hardware.

15. A system for testing a data communication architecture comprising:

means for injecting a packet into a scalable computer network via a system interconnect, and

means for monitoring a response to said packet.