Method and system for managing cache injection in a multiprocessor system

• US 20060064518A1
• Filed: 09/23/2004
• Published: 03/23/2006
• Est. Priority Date: 09/23/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rajamony, Ramakrishnan, Gheith, Ahmed, Sinharoy, Balaram, Shafi, Hazim, Hochschild, Peter Heiner, Bohrer, Patrick Joseph
• Granted Patent: US 8,255,591 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.

Claims

1. A method for reducing processing time associated with a direct memory access (DMA) transfer within processing system including multiple processors, said method comprising:

initiating said DMA transfer to a DMA transfer target memory image within a DMA transfer target memory over a bus;

determining in a cache controller managing a cache memory associated with a particular one of said multiple processors that said DMA transfer is occurring on said bus;

responsive to determining that said DMA transfer is occurring, copying data being transferred in said DMA transfer to a cache line in said cache memory during said DMA transfer; and

targeting said particular processor for executing a routine that accesses memory addresses of said DMA transfer target memory image, whereby said particular processor processes data transferred by said DMA transfer.

2. The method of claim 1, wherein said targeting comprises identifying said particular processor subsequent to completion of said DMA transfer, and further comprising queuing said routine for execution by said particular processor.

3. The method of claim 2, further comprising generating an interrupt in response to completion of said DMA transfer, and wherein said identifying and queuing are performed in response to said interrupt, whereby another processor handling said interrupt processor schedules execution of said routine on said particular processor.

5. The method of claim 1, wherein said targeting comprises:

selecting said particular processor prior to said initiating;

selecting said cache memory in conjunction with selecting said particular processor; and

directing execution of said routine to said particular processor.

6. The method of claim 5, wherein said processing system is an non-uniform memory access (NUMA) multiprocessor system and wherein said particular processor is selected in conformity with a latency between said cache memory and said DMA transfer target memory.

7. The method of claim 5, further comprising generating an interrupt in response to completion of said DMA transfer, and wherein said directing is performed by setting an interrupt map directing handling of said interrupt to said particular processor.

8. The method of claim 7, wherein said interrupt map is an interrupt register mask in a programmable interrupt controller, and wherein said setting is performed by programming said programmable interrupt controller.

9. The method of claim 1, wherein said copying is performed in response to said cache controller determining that said cache line is present and valid in said cache memory, whereby said cache line is maintained in a valid state at a time of execution of said DMA completion routine.

10. The method of claim 1, wherein said copying is performed in response to said cache controller detecting that said cache line is not present in said cache memory, and further comprising allocating a line for storing said cache line in said cache memory prior to said copying.

4. The method of claim 4, wherein said processing system is a non-uniform memory access (NUMA) multiprocessor system and further comprising selecting said particular processor in conformity with a latency between said cache memory and said DMA transfer target memory.

11. A multiprocessor system, comprising:

a plurality of processors each coupled to an associated one of a plurality of cache memories;

at least one cache controller coupled to said associated cache memories, said at least one cache controller including a bus snooper for observing transfers on at least one bus coupling said cache memories to a memory and a transfer circuit for transferring data to cache lines managed by said cache controller in response to detecting that a direct memory access (DMA) transfer is taking place to said memory; and

an executive program resident in a program memory coupled to an executive processor of said multiprocessor system, comprising program instructions for;

initiating said DMA transfer to said memory, and

targeting a particular one of said plurality of processors for executing a routine that accesses said data, whereby said particular processor processes data transferred by transfer circuit into said cache memory associated with said particular processor.

12. The multiprocessor system of claim 11, wherein said executive processor is one of said plurality of processors.

13. The multiprocessor system of claim 11, wherein said executive program further comprises program instructions for:

identifying said particular processor subsequent to completion of said DMA transfer; and

queuing said routine for execution by said particular processor.

14. The multiprocessor system of claim 13, wherein said multiprocessor system is a non-uniform memory access (NUMA) multiprocessor system and wherein said executive program further comprises program instructions for selecting said particular processor in conformity with a level of transfer latency between said cache memory and said memory.

15. The multiprocessor system of claim 11, wherein said executive program further comprises program instructions for:

selecting said particular processor prior to said initiating, whereby said cache memory is selected by selection of said particular processor; and

directing execution of said routine to said particular processor.

16. The multiprocessor system of claim 15, wherein said multiprocessor system is a non-uniform memory access (NUMA) multiprocessor system and wherein program instructions for selecting select said particular processor in conformity with a transfer latency between said cache memory and said memory.

17. The multiprocessor system of claim 15, wherein said executive program further comprises program instructions for handling an interrupt generated in response to completion of said DMA transfer, and wherein said program instructions for directing set an interrupt map directing handling of said interrupt to said particular processor.

18. The multiprocessor system of claim 17, wherein said interrupt map is an interrupt register mask in a programmable interrupt controller, and wherein said program instructions for setting program said programmable interrupt controller.

19. The multiprocessor system of claim 11, wherein said bus snooper detects a hint bit present in a bus state decode of said at least one bus that indicates that write to said memory are part of said DMA transfer, and wherein said transfer circuit transfers data to said cache line in response to said bus snooper detecting that said hint bit is present.

20. The multiprocessor system of claim 11, wherein said bus snooper detects that an address of a write to said memory on said at least one bus indicates that said write is part of said DMA transfer, and wherein said transfer circuit transfers data to said cache line in response to said bus snooper detecting that said address indicates that said write is part of said DMA transfer.

21. The multiprocessor system of claim 20, wherein said bus snooper further determines that an address of a write to said memory on said at least one bus indicates that said DMA transfer is targeted for access by said particular processor, and wherein said transfer circuit transfers said values to said cache associated with said particular processor in response to a result of said address determining.

22. The multiprocessor system of claim 20, wherein said bus snooper further determines a processor/cache identifier from a bus state decode associated with said write, and wherein said transfer circuit transfers said values to said cache associated with said particular processor in conformity with said identifier.

23. A computer program product comprising signal-bearing media encoding program instructions forming part of an executive program for execution by a processor within a multiprocessor system, said multiprocessor system including a cache controller with a cache injection feature that loads values into a cache memory during a direct memory access (DMA) transfer to a memory within said multiprocessor system, said values being at least a portion of data transferred by said DMA transfer, and said program instructions comprising program instructions for:

initiating said DMA transfer; and

targeting a particular one of a plurality of processors of said multiprocessor system for execution of a routine that accesses said values, wherein said particular processor is a processor associated with said cache memory, whereby said particular processor processes said values.

24. The computer program product of claim 23, wherein said program instructions further comprise program instructions for:

identifying said particular processor subsequent to completion of said DMA transfer; and

queuing said routine for execution by said particular processor.

25. The computer program product of claim 24, wherein said multiprocessor system is a non-uniform memory access (NUMA) multiprocessor system and wherein said program instructions further comprise program instructions for selecting said particular processor in conformity with a level of transfer latency between said cache memory and said memory.

26. The computer program product of claim 23, wherein said program instructions further comprise program instructions for:

selecting said particular processor prior to said initiating, whereby said cache memory is selected by selection of said particular processor; and

directing execution of said routine to said particular processor.

27. The computer program product of claim 26, wherein said multiprocessor system is a non-uniform memory access (NUMA) multiprocessor system and wherein program instructions for selecting select said particular processor in conformity with a transfer latency between said cache memory and said memory.

28. The computer program product of claim 26, wherein said program instructions further comprise program instruction for handling an interrupt generated in response to completion of said DMA transfer, and wherein said program instructions for directing set an interrupt map directing handling of said interrupt to said particular processor.

29. The computer program product of claim 28, wherein said interrupt map is an interrupt register mask in a programmable interrupt controller, and wherein said program instructions for setting program said programmable interrupt controller.