Method of forming gate by using layer-growing process and gate structure manufactured thereby

• US 20060065893A1
• Filed: 09/23/2005
• Published: 03/30/2006
• Est. Priority Date: 09/24/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jin, You-seung, Maeda, Shigenobu
• Application Number:
  US11/233,806
• Publication Number:
  US 20060065893A1
• Time in Patent Office: Days
• US Class Current: 257/65
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

Provided are a method of forming a gate by using layer growth, and a gate structure formed thereby. A gate dielectric layer and a seed layer are sequentially formed on a substrate, and then a mask is used to selectively grow a gate layer on the seed layer. An exposed portion of the seed layer surrounding the gate layer, and the gate layer, are isotropically etched to form a gate.

Claims

1. A method of forming a gate of a transistor, the method comprising:

forming a gate dielectric layer on a substrate;

forming a seed layer on the gate dielectric layer;

forming a mask on the seed layer to selectively grow a gate layer;

selectively growing the gate layer on a portion of the seed layer exposed by the mask;

selectively removing the mask; and

isotropically etching exposed portions of the seed layer and the gate layer to form a gate such that the gate has a smaller line width than the gate layer.

2. The method of claim 1, wherein the seed layer comprises polycrystalline silicon.

3. The method of claim 1, wherein the seed layer comprises silicon germanium.

4. The method of claim 1, wherein the seed layer has a thickness of a few to a few tens of nanometers.

5. The method of claim 1, wherein the mask comprises at least one of silicon oxide, Si₃N₄, and SiON.

6. The method of claim 1, wherein the gate layer is formed by epitaxtially growing polycrystalline silicon on the seed layer.

7. The method of claim 1, wherein the gate layer is formed by epitaxtially growing silicon germanium on the seed layer.

8. The method of claim 1, wherein the gate is formed by chemical dry etching-(CDE).

9. The method of claim 1, wherein the gate is formed by at least one of dry etching and wet etching.

10. A method of forming a gate of a transistor, the method comprising:

forming a gate dielectric layer on a substrate;

forming a seed layer on the gate dielectric layer;

forming on the seed layer a mask having an open region exposing a portion of the seed layer to selectively grow a gate layer on the exposed portion of the seed layer;

forming spacers covering a portion of the exposed portion of the seed layer on sidewalls of the open region of the mask such that a line width of the exposed portion of the seed layer is less than an upper line width of the open region;

selectively growing the gate layer on the portion of the seed layer exposed by the mask and the spacer;

selectively removing the mask and the spacer; and

isotropically etching exposed portions of the seed layer and the gate layer to form a gate such that a lower line width of the gate is less than a line width of the gate layer and an upper line width of the gate is greater than the lower line width of the gate.

11. The method of claim 10, wherein the seed layer comprises polysilicon silicon.

12. The method of claim 10, wherein the seed layer comprises silicon germanium.

13. The method of claim 10, wherein the mask comprises at least one of silicon oxide, Si₃N₄, and SiON.

14. The method of claim 13, wherein the spacer and the mask are formed of identical insulating materials.

15. The method of claim 10, wherein the gate layer is formed by epitaxtially growing polycrystalline silicon on the seed layer.

16. The method of claim 10, wherein the gate layer is formed by epitaxtially growing silicon germanium on the seed layer.

17. The method of claim 10, wherein the gate is formed by chemical dry etching (CDE).

18. A gate of a transistor, the gate comprising:

a seed layer formed on a gate dielectric layer on a substrate; and

a gate layer formed by selectively growing silicon germanium on the seed layer.

19. A gate of a transistor, the gate comprising:

a seed layer formed on a gate dielectric layer on a substrate; and

a gate layer formed by selectively growing silicon germanium on the seed layer, wherein a lower line width of the gate layer is less than an upper line width of the gate layer.

20. The gate of claim 19, wherein the seed layer is formed of polycrystalline silicon.