Vertical MOSFET
First Claim
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1. A vertical MOSFET comprising:
- a gate electrode formed inside a trench in a semiconductor layer;
an interlayer insulating film formed above the semiconductor layer;
a source electrode formed above the interlayer insulating film and electrically connected to a source region of the semiconductor layer through a conductive plug filled in a contact hole of the interlayer insulating film; and
a protection diode having one end electrically connected to the source electrode and another end connected to the gate electrode through a gate metal line and including a plurality of PN junctions, wherein the protection diode is formed inside a depressed portion in the semiconductor layer.
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Abstract
A vertical MOSFET includes a gate electrode formed inside a trench in a semiconductor layer, an interlayer insulating film formed above the semiconductor layer, a source electrode formed above the interlayer insulating film and electrically connected to a source region of the semiconductor layer through a conductive plug filled in a contact hole of the interlayer insulating film, and a protection diode having one end electrically connected to the source electrode and another end connected to the gate electrode through a gate metal line and including a plurality of PN junctions. The protection diode is formed inside a depressed portion in the semiconductor layer.
22 Citations
5 Claims
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1. A vertical MOSFET comprising:
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a gate electrode formed inside a trench in a semiconductor layer;
an interlayer insulating film formed above the semiconductor layer;
a source electrode formed above the interlayer insulating film and electrically connected to a source region of the semiconductor layer through a conductive plug filled in a contact hole of the interlayer insulating film; and
a protection diode having one end electrically connected to the source electrode and another end connected to the gate electrode through a gate metal line and including a plurality of PN junctions, wherein the protection diode is formed inside a depressed portion in the semiconductor layer. - View Dependent Claims (2, 3, 4, 5)
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Specification