Insulated gate semiconductor device and manufacturing method of the same

• US 20060065926A1
• Filed: 09/21/2005
• Published: 03/30/2006
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Iwata, Satoshi, Yanagida, Masamichi, Kubo, Hirotoshi, Onda, Masahito, Saito, Hiroaki, Tojo, Junichiro
• Granted Patent: US 7,413,954 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.

Claims

1. An insulated gate semiconductor device comprising:

a semiconductor substrate comprising a drain region of a first general conduction type;

a channel layer of a second general conduction type disposed on the drain region;

a trench which penetrates the channel layer and reaches the semiconductor substrate;

a first semiconductor layer disposed at a bottom portion of the trench;

an insulating film disposed on an inner wall of the trench;

a second semiconductor layer disposed in the trench so as to be on the first semiconductor layer; and

a source region of the first general conduction type disposed on the channel layer and adjacent the trench.

2. The insulated gate semiconductor device of claim 1, wherein the first semiconductor layer is made of a non-doped polysilicon.

3. The insulated gate semiconductor device of claim 1, wherein the first semiconductor layer is disposed below the channel layer.

4. The insulated gate semiconductor device of claim 1, wherein the insulating film extends between the first semiconductor layer and the second semiconductor layer.

5. The insulated gate semiconductor device of claim 4, wherein the first semiconductor layer is covered with the insulating film.

6. The insulated gate semiconductor device of claim 1, wherein the insulating film comprises a first insulating film covering a sidewall and a bottom portion of the first semiconductor layer and a second insulating film covering a top portion of the first semiconductor layer.

7. A method of manufacturing an insulated gate semiconductor device, comprising:

forming on a semiconductor substrate of a first general conduction type a channel layer of a second general conduction type;

forming a trench which penetrates the channel layer and reaches the semiconductor substrate;

forming an insulating film on an inner wall of the trench;

forming a first semiconductor layer at a bottom of the trench;

forming in the trench a second semiconductor layer that is disposed on the first semiconductor layer; and

forming a source region of the first general conduction type in a surface of the channel layer and adjacent the trench.

8. The method of claim 7, wherein the forming of the first semiconductor layer comprises a deposition of a non-doped polysilicon.

9. A method of manufacturing an insulated gate semiconductor device, comprising:

forming on a semiconductor layer of a first general conduction type a channel layer of a second general conduction type;

forming a trench which penetrates the channel layer and reaches the semiconductor layer;

forming a first insulating film on an inner wall of the trench;

forming a first semiconductor layer at a bottom of the trench;

forming a second insulating film on the inner wall of the trench;

forming in the trench a second semiconductor layer that is disposed on the first semiconductor layer; and

forming a source region of the first general conduction type in a surface of the channel layer and adjacent the trench.

10. The method of claim 9, wherein the forming of the first semiconductor layer comprises a deposition of a non-doped polysilicon.

11. The method of claim 9, wherein the forming of the first semiconductor layer is performed between the forming of the first insulating film and the forming of the second insulating film.

12. The method of claim 11, further comprising removing part of the first insulating film prior to the forming of the second insulating film.

13. An insulated gate semiconductor device comprising:

a semiconductor substrate comprising a drain region, a channel layer disposed on the drain region and a source region disposed on the channel layer; and

a trench formed in the semiconductor substrate so that a channel is formed vertically along the trench between the drain region and the source region,

wherein the trench is separated by an insulating film into a first semiconductor portion and a second semiconductor portion.

14. The insulated gate semiconductor device of claim 13, wherein the first semiconductor portion is disposed under the second semiconductor portion so that the first semiconductor portion is located within the drain region.