Fault dictionaries for integrated circuit yield and quality analysis methods and systems

• US 20060066338A1
• Filed: 09/06/2005
• Published: 03/30/2006
• Est. Priority Date: 09/06/2004
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Chen, Gang, Sharma, Manish, Rajski, Janusz, Keim, Martin, Tang, Huaxing, Tamarapalli, Nagesh
• Granted Patent: US 7,987,442 B2
• Time in Patent Office: Days
• US Class Current: 714/738
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12
• CPC Class Codes: G01R 31/2846 using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G06F 11/2273 Test methods

Abstract

Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.

Claims

1. A computer-implemented method, comprising:

generating one or more fault dictionaries for identifying one or more defect candidates from corresponding observation point combinations, the observation point combinations indicating the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern, the act of generating the one or more fault dictionaries comprising,

for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and

for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.

2. The method of claim 1, wherein the one or more first indicators comprise unique IDs associated with the test patterns detecting the first defect candidate.

3. The method of claim 1, wherein the one or more first indicators comprise unique IDs associated with the observation point combinations for the test patterns detecting the first defect candidate.

4. The method of claim 1, wherein the first defect candidate and the second defect candidate are in a fan-out free region of the circuit-under-test.

5. The method of claim 4, wherein the first defect candidate is located at a stem of the fan-out free region.

6. The method of claim 1, further comprising identifying one or more defect candidates during production testing of the circuits-under-test using the generated one or more fault dictionaries.

7. The method of claim 6, further comprising performing at least one of the acts of incrementally diagnosing or incrementally simulating one or more possible defects not identified by the generated one or more fault dictionaries.

8. The method of claim 7, further comprising updating the generated one or more fault dictionaries with results from the performance of one or more of the acts of incrementally diagnosing or incrementally simulating.

9. The method of claim 7, further comprising at least one of the acts of updating one or more defect extraction rules or updating one or more of the design manufacturing rules based at least in part on results from the acts of incrementally diagnosing or incrementally simulating.

10. The method of claim 1, wherein the circuits-under-test comprise integrated circuits designed for functional use in electronic devices.

11. The method of claim 1, wherein the number of test patterns detecting the first defect candidate is limited to at least one of the following:

(a) a predetermined value;

or (b) a user-selected value.

12. The method of claim 1, wherein the test patterns detecting the first defect candidate comprise test patterns using static fault models and test patterns using dynamic fault models.

13. The method of claim 12, wherein the one or more fault dictionaries comprise at least a first fault dictionary and a second fault dictionary, and wherein fault dictionary information concerning the test patterns using static fault model is stored in the first fault dictionary and fault dictionary information concerning the test patterns using dynamic fault models is stored in the second fault dictionary.

14. The method of claim 1, wherein at least some of the test patterns detecting the second defect candidate use a different type of fault model than used to detect the first defect candidate.

15. The method of claim 1, wherein the observation point combinations correspond to compacted test responses output from a compactor in the circuit-under-test.

16. The method of claim 1, further comprising storing one or more of the following properties for at least the first defect candidate:

a defect identifier that distinguishes the defect candidate from other potential defects;

a derived rule identifier that identifies the defect extraction rule used to extract the first defect candidate;

a design manufacturing rule identifier that identifies the design manufacturing rule from which the defect extraction rule used to extract the first defect candidate was derived;

one or more physical properties of the fist defect candidate in the physical layout of the integrated circuit design;

a physical location of the first defect candidate in the physical layout of the integrated circuit design; and

a ranking of the first defect candidate relative to other potential defects.

17. One or more tangible computer-readable media comprising computer-executable instructions for causing a computer to perform the method of claim 1.

18. At least one computer programmed to carry out the method of claim 1.

19. A computer-implemented method, comprising:

receiving a list of potential defects in an integrated circuit layout identified by using extraction rules derived at least partially from a set of design manufacturing rules, the design manufacturing rules comprising design parameters for manufacturing an integrated circuit;

producing a set of test patterns by;

(a) selecting from previously generated test patterns one or more test patterns that detect at least some of the identified potential defects;

(b) generating one or more test patterns that explicitly target at least some of the identified potential defects;

or both (a) and (b); and

generating at least one fault dictionary indicative of one or more failing test responses to an associated test pattern and one or more potential defects respectively associated with the failing test responses.

20. The method of claim 19, wherein the at least one fault dictionary is a compressed fault dictionary, and wherein the act of generating the at least one fault dictionary comprises using one or more bit masks to represent the failing test responses associated with a respective potential defect.

21. The method of claim 19, wherein the at least one fault dictionary is a compressed fault dictionary, and wherein the act of generating the at least one fault dictionary comprises using detection information of one or more pseudo faults to represent the detection information of a respective potential defect.

22. The method of claim 19, further comprising:

receiving test-result data comprising failing test responses obtained during testing of the integrated circuits using at least a portion of the test patterns in the set of test patterns; and

applying the at least one fault dictionary to the test-result data in order to diagnose potential defects associated with one or more of the failing test responses.

23. The method of claim 22, further comprising using an incremental diagnosis or incremental simulation procedure to diagnose potential defects that are not diagnosable using the at least one fault dictionary.

24. The method of claim 22, further comprising statistically determining probabilities that potential defects are actually causing the failing test responses using diagnostic results obtained from the application of the at least one fault dictionary.

25. One or more tangible computer-readable media comprising computer-executable instructions for causing a computer to perform the method of claim 19.

26. At least one computer programmed to carry out the method of claim 19.

27. A method of testing integrated circuits, comprising:

determining a set of defect extraction rules at least partially derived from a first set of design manufacturing rules, the defect extraction rules defining plural subcategories of at least one category of potential defects identified by the design manufacturing rules;

extracting potential defects by applying at least a subset of the defect extraction rules to an electronic description of the physical layout of an integrated circuit, the extracted potential defects falling into at least one of the subcategories;

defining plural circuit tests that indicate the presence of potential defects in the manufactured integrated circuits, the circuit tests each comprising a set of circuit stimuli to be applied to manufactured integrated circuits containing the integrated circuit; and

storing for at least a plurality of circuit tests, the potential defect or defects detected by the circuit test and failing test responses that, if observed, would indicate the presence of the potential defect or defects detected by the circuit test.

28. The method of claim 27, further comprising applying the circuit tests to the manufactured integrated circuits, capturing test responses, and determining failing integrated circuits that produce one or more test responses that fail one or more of the applied circuit tests.

29. The method of claim 28, further comprising, for one or more of the failing integrated circuits:

identifying one or more circuit tests that produced the failing test response or responses; and

comparing one or more of the failing test responses associated with an identified circuit test with stored failing test responses associated with the identified circuit test to thereby attempt to deduce one or more defects that potentially caused the failing test response.

30. The method of claim 29, wherein the amount of data stored when storing the results of such comparison is compressed or limited by at least, for each potential defect, only storing k detecting failing test responses, wherein k designates the maximum number of failing test responses for the potential defect that are stored.

31. The method of claim 29, further comprising:

collecting and analyzing information concerning the repetitive identification of the occurrence of potential types of defects in the failing integrated circuits; and

reporting data representing the probability that certain types of defects are causing the failing test responses.

32. The method of claim 31, wherein the reporting comprises generating a graphical representation of the data.

33. The method of claim 32, wherein the graphical representation is a pareto chart.

34. The method of claim 27, wherein the act of storing further comprises storing one or more of the following properties associated with a respective potential defect:

a defect identifier that distinguishes the respective potential defect from other potential defects;

a derived rule identifier that identifies the defect extraction rule used to extract the potential defect;

a design manufacturing rule identifier that identifies the design manufacturing rule on which the defect extraction rule is based;

one or more physical properties of the respective potential defect in the physical layout of the integrated circuit design;

physical location of the respective potential defect in the physical layout of the integrated circuit design; and

a ranking of the respective potential defect relative to other potential defects.

35. The method of claim 27, wherein the set of defect extraction rules also comprises at least one potential defect identified by a worst case defect identifier as a worst case defect.

36. The method of claim 27, wherein the act of storing comprises the act of generating a defect comparison dictionary describing failing test responses by an identification of the potential defect the fault was derived from, the type of potential fault, the test patterns detecting the potential fault, and the observation points for each detecting test pattern.

37. The method of claim 36, comprising the act of modifying the stored information by performing one or more of the following:

(a) adding a potential defect not previously found in the dictionary;

(b) adding at least one test associated with the potential defect not previously found in the dictionary;

(c) adding at least one expected failing test response expected to be received in the event the potential defect not previously found in the dictionary is present in a tested integrated circuit, or (d) deleting an entry in the dictionary associated with a test response that has not detected a failing circuit after a predetermined or user-selected number of circuit tests.

38. The method of claim 36, further comprising:

comparing failing test responses associated with one of the circuit tests with failing test responses associated with the circuit test stored in the dictionary to determine the existence of potential defects and the types of such defects; and

storing the results of such comparison.

39. The method of claim 38, comprising the act of identifying integrated circuits that fail due to miscellaneous potential defects not identified by the comparison and repeating the acts of claim 27 with a modified set of defect extraction rules to target at least one of the miscellaneous potential defects.

40. The method of claim 38, further comprising:

diagnosing a miscellaneous potential defect not identified by the comparison to identify the miscellaneous potential defect; and

modifying the dictionary to include the identified miscellaneous potential defect.

41. The method of claim 40, wherein the diagnosing is performed using an effect-cause-based diagnosis procedure.

42. One or more tangible computer-readable media comprising computer-executable instructions for causing a computer to perform the method of claim 27.

43. At least one computer programmed to carry out the method of claim 27.

44. A computer-implemented method, comprising:

receiving test-result information from tests of multiple integrated circuits, the test-result information comprising failing test responses associated with respective test patterns applied during the tests;

using a fault dictionary to diagnose at least a portion of the test-result information in order to identify potential defects that may have caused one or more of the failing test responses; and

using at least one of an incremental diagnosis or incremental simulation procedure to diagnose test-result information that was not diagnosable using the fault dictionary.

45. The method of claim 44, further comprising, from diagnostic results produced using the fault dictionary, determining probabilities that one or more of the potential defects actually caused the integrated circuit failures and reporting the probabilities.

46. The method of claim 45, further comprising performing one or more of the following based at least in part on the reported probabilities:

(a) adjusting one or more design manufacturing rules;

(b) adjusting one or more defect extraction rules;

or (c) providing recommended modifications of one or more features in the integrated circuit.

47. The method of claim 44, wherein the fault dictionary is a compressed fault dictionary using one or more bit masks to associate one or more failing test responses to respective potential defects.

48. One or more tangible computer-readable media comprising computer-executable instructions for causing a computer to perform the method of claim 44.

49. At least one computer programmed to carry out the method of claim 44.