Low power outpur driver

• US 20060066354A1
• Filed: 09/26/2005
• Published: 03/30/2006
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: ICS Incorporated (Charys Holding Company Incorporated)
• Inventors: Isik, Tacettin, Clementi, Daniel M., Poitras, Louis F.
• Granted Patent: US 7,342,420 B2
• Time in Patent Office: Days
• US Class Current: 326/86
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

Claims

1. A low power output driver comprising:

(a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage;

(b) a first driver input that receives a first logic signal;

(c) a second driver input that receives a second logic signal;

(d) a first driver output that outputs a first output signal;

(e) a second driver output that outputs a second output signal;

(f) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage V_L and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;

(g) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;

(h) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the reduced voltage V_L and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and

(i) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input,

when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage and the second driver output is pulled down to the internal ground, and

when the second input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

2. The low power output driver of claim 1, wherein the regulated reduced voltage source includes:

(a1) a voltage source input that receives the supply voltage V_DD; and

(a2) a voltage source output that outputs the regulated reduced voltage V_L.

3. The low power output driver of claim 2, wherein the regulated reduced voltage source further includes:

(a3) a voltage source MOS having a gate, a source and a drain, the source and the drain of the voltage source MOS being electrically coupled between the voltage source input and voltage source output; and

(a4) an operational amplifier having a non-inverting input, an inverting input and an amplifier output, the non-inverting input being electrically coupled to an internal reference, the inverting input being electrically coupled to the voltage source output and the amplifier output being electrically coupled to the gate of the voltage source NMOS.

4. The low power output driver of claim 2, wherein the regulated reduced voltage source further includes:

(a3) a voltage source bipolar transistor, the voltage source bipolar transistor being electrically coupled between the voltage source input and voltage source output; and

(a4) an operational amplifier having a non-inverting input, an inverting input and an amplifier output, the non-inverting input being electrically coupled to an internal reference, the inverting input being electrically coupled to the voltage source output and the amplifier output being electrically coupled to the gate of the voltage source NMOS.

5. The low power output driver of claim 2, wherein the inverting input of the operational amplifier is capacitively coupled to the internal ground.

6. The low power output driver of claim 2, wherein the internal reference includes one of a bandgap reference, a resistance voltage divider, an external reference and an external bandgap.

7. The low power output driver of claim 1, wherein the supply voltage is between about 1.0 and about 6.0 volts direct current (VDC) and the reduced voltage is between about 0.1 and about 1.5 VDC.

8. The low power output driver of claim 1, wherein the supply voltage is about 3.3 volts direct current (VDC) and the reduced voltage is about 0.75 VDC.

9. The low power output driver of claim 1, wherein the reduced voltage source and the first, second, third and fourth NMOS are disposed in a common integrated circuit (IC).

10. The low power output driver of claim 1, wherein the first, second, third and fourth NMOS are disposed in a common integrated circuit (IC) and the reduced voltage source is disposed external to the IC.

11. The low power output driver of claim 1, wherein the first and second driver outputs form a voltage source.

12. The low power output driver of claim 1, wherein the first logic signal and the second logic signal are complementary.

13. A low power output driver system comprising:

(a) a reference voltage supply;

(b) a first voltage regulator that receives reference voltage supply and outputs a first regulated voltage;

(c) a second voltage regulator that receives reference voltage supply and outputs a second regulated voltage;

(d) a first low power output driver; and

(e) a second low power output driver,

each of the first and second low power output drivers including;

(i) a first driver input that receives a first logic signal;

(ii) a second driver input that receives a second logic signal;

(iii) a first driver output that outputs a first output signal;

(iv) a second driver output that outputs a second output signal;

(v) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the respective first and second regulated voltage and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;

(vi) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;

(vii) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the respective first and second regulated voltage and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and

(viii) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input.

14. The low power output driver system of claim 13, further comprising:

(f) a third voltage regulator that receives reference voltage supply and outputs a third regulated voltage;

(g) a third low power output driver, the third low power output driver including;

(i) a first driver input that receives the first logic signal;

(ii) a second driver input that receives the second logic signal;

(iii) a first driver output that outputs a first output signal;

(iv) a second driver output that outputs a second output signal;

(v) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the third regulated voltage and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;

(vi) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;

(vii) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the third regulated voltage and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and

(viii) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input.

15. The low power output driver system of claim 14, wherein the first, second and third regulated voltages are different voltage potentials.

16. The low power output driver system of claim 14, wherein at least two of the first, second and third regulated voltages are approximately the same voltage potential.

17. The low power output driver system of claim 13, wherein the first and second regulated voltages are different voltage potentials.

18. The low power output driver system of claim 13, wherein the first and second regulated voltages are approximately the same voltage potential.

19. The low power output driver system of claim 13, further comprising:

a plurality of low power output drivers coupled to the first voltage regulator; and

a plurality of low power output drivers coupled to the second voltage regulator.