Revenue meter with power quality features

• US 20060066456A1
• Filed: 08/22/2005
• Published: 03/30/2006
• Est. Priority Date: 08/09/1999
• Status: Active Grant

• Current Assignee: Colin N. Gunn, Constantine A. Antoniou, Michael E. Teachman, Piotr B. Przydatek, Rene T. Jonker
• Original Assignee: Colin N. Gunn, Constantine A. Antoniou, Michael E. Teachman, Piotr B. Przydatek, Rene T. Jonker
• Inventors: Gunn, Colin N., Przydatek, Piotr B., Teachman, Michael E., Jonker, Rene T., Antoniou, Constantine A.
• Granted Patent: US 7,342,507 B2
• Time in Patent Office: Days
• US Class Current: 340/870.20
• CPC Class Codes: G01R 21/133 by using digital technique

Abstract

Power quality detection, monitoring, reporting, recording and communication in a revenue accuracy electrical power meter is disclosed. Transient events are detected by monitoring the wave shape of the electrical power and comparing deviations to a known threshold. Sags and Swells are detected by computing root mean square value over a rolling window and comparing the computed value with a known threshold. Harmonic frequencies and symmetrical components are quantified by a known algorithm and compared with a known threshold. Incoming waveforms are stored to memory. All recorded and computed data is moved to non-volatile storage via direct memory access transfer in the event that a power quality event jeopardizes the operating power of the meter. Further, the meter provides a power supply utilizing high and low capacitive storage banks to supply sufficient energy to survive short duration power quality events which jeopardize the meter'"'"'s operating power.

Claims

1. In an energy meter for measuring the delivery of electrical energy through an electric circuit, said meter comprising first and second processors, first and second data busses, first and second memories, at least one bus arbiter responsive to said first and second processors and coupled with said first and second data busses and at least one transfer controller responsive to said first and second processors and coupled with said at least one bus arbiter, wherein each of said processors are coupled with a respective each said data busses and each of said data busses are coupled with a respective each of said memories, a method of transferring data between said first and second memories comprising:

requesting, from said first processor to said at least one transfer controller, at least one data transfer between said first memory and said second memory;

signaling said first processor by said at least one transfer controller to initiate said data transfer;

releasing control of said first data bus by said first processor;

signaling by said first processor to said at least one bus arbiter to couple said first data bus to said second data bus;

coupling said first data bus to said second data bus;

signaling by said at least one bus arbiter to said at least one transfer controller that said first and second data busses are coupled and said first processor is ready for said data transfer;

transferring data between said first memory and said second memory under control of said at least one transfer controller;

signaling by said at least one transfer controller to said at least one bus arbiter to isolate said first data bus from said second data bus upon completion of said data transfer;

signaling to said first processor from said at least one bus arbiter that said data transfer is complete and said first and second data busses are isolated;

acquiring control of said first data bus by said first processor; and

signaling said second processor by said at least one transfer controller that said data transfer is complete.