Circuit configuration for analog/digital conversion

• US 20060066465A1
• Filed: 09/06/2005
• Published: 03/30/2006
• Est. Priority Date: 09/25/2004
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Fehrenbacher, Berthold, Koerner, Gotthilf, Breitmaier, Axel
• Granted Patent: US 7,176,816 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03M 1/1076 Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
• CPC Class Codes: H03M 1/1225 using time-division multiplexing

Abstract

A circuit configuration for converting analog signals to digital signals, having a multiplexer which has a plurality of analog signal inputs, an address input that is several bits wide and an output, and which is configured to connect one of the analog signal inputs to the output when an address assigned to the respective analog signal input is applied to the address input, and having an analog/digital converter, whose input is connected to the output of the multiplexer in order to digitize the respective analog signal emitted at the output. The circuit configuration includes at least one test signal source for supplying a test signal to a subset of the analog signal inputs of the multiplexer. In addition, an address is assigned to each of the analog signal inputs of this subset, of whose bits one has a first binary value, and all the others have a second binary value that is different from the first.

Claims

1. A circuit configuration for converting analog signals to digital signals, comprising:

a multiplexer having a plurality of analog signal inputs, an address input that is several bits wide and an output, the multiplexer being configured to connect one of the analog signal inputs to the output when an address assigned to the respective analog signal input is applied to the address input;

an analog/digital converter having an input connected to the output of the multiplexer to digitize the respective analog signal emitted at the output of the multiplexer;

at least one test signal source configured to supply a test signal to a subset of the analog signal inputs of the multiplexer; and

to the analog signal inputs of the subset, in each case an address comprised of bits is assigned, of whose bits one has a first binary value and all the others have a second binary value that is different from the first binary value.

2. The circuit configuration as recited in claim 1, wherein the test signal source includes a voltage divider for picking off a partial voltage of an operating voltage of the circuit configuration as a test signal.

3. The circuit configuration as recited in claim 1, wherein each output of the test signal source that supplies a test signal is permanently wired to a corresponding analog signal input of the subset.

4. The circuit configuration as recited in claim 1, wherein test signals, present at respectively different analog signal inputs of the subset, supply different results of the digitizing in the analog/digital converter.

5. The circuit configuration as recited in claim 1, further comprising:

a comparator, a first input of the comparator being connected to an output of the analog/digital converter.

6. The circuit configuration as recited in claim 5, further comprising:

a setpoint device configured to supply to a second input of the comparator a setpoint for a result of the digitizing of a test signal by the analog/digital converter.

7. The circuit configuration as recited in claim 6, further comprising:

an error register into which an error entry is made if the comparator establishes a difference between a result of the digitizing of the test signal and a setpoint value assigned to the test signal.

8. The circuit configuration as recited in claim 7, wherein the error entry is made if the difference exceeds a specified limit that is different from zero.

9. The circuit configuration as recited in claim 1, wherein the circuit configuration is configured to convert the analog signals, present at the inputs of the multiplexer, at least one of sequentially and cyclically.

10. The circuit configuration as recited in claim 9, further comprising:

a memory having storage locations assigned to the inputs of the multiplexer to store the result of the digitizing of one of the analog signals by the analog/digital converter in the respectively assigned storage location, the circuit configuration being configured to determine if a digital value generated from the test signals is read out from the memory, and to replace the read-out digital value in the respective storage location by a respectively specified digital value.

11. The circuit configuration as recited in claim 1, further comprising:

a reference voltage source coupled between the output of the multiplexer and the input of the analog/digital converter to supply a reference voltage to the input of the analog/digital converter.