Charge-trapping memory cell

• US 20060067122A1
• Filed: 09/29/2004
• Published: 03/30/2006
• Est. Priority Date: 09/29/2004
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Verhoeven, Martin
• Application Number:
  US10/952,711
• Publication Number:
  US 20060067122A1
• Time in Patent Office: Days
• US Class Current: 365/185.50
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence

Abstract

The channel region is slightly elevated with respect to the source and drain regions to form steps in the semiconductor surface, which are covered by a dielectric memory layer sequence provided for charge-trapping, the memory layer sequence comprising a lower confinement layer, a memory layer and an upper confinement layer. Electrons that are accelerated from source to drain are more probably scattered on a straight trajectory, on which they pass the lower confinement layer and are trapped in the memory layer. This memory cell aims at improving the speed of write operations.

Claims

1. A charge-trapping memory cell, comprising:

a semiconductor body with a main surface;

a source region, a channel region and a drain region disposed at the main surface, the source region being spaced from the drain region by the channel region, wherein the source region and the drain region are doped to have the same conductivity type;

a memory layer sequence of dielectric materials provided for charge-trapping and comprising a lower confinement layer, a memory layer and an upper confinement layer, the memory layer sequence being arranged on the main surface at least in areas that cover junctions between the source region and the channel region and between the drain region and the channel region, wherein main surface is structured so that a plane formed by the main surface in the area of the channel region intersects the memory layer sequence; and

a gate electrode arranged adjacent the memory layer sequence and provided to control the channel.

2. The charge-trapping memory cell as claimed in claim 1, wherein:

the main surface is elevated at a region of the channel region thereby forming a first step at the junction between the source region and the channel region and a second step at the junction between the drain region and the channel region;

the first and second steps are covered by the memory layer sequence; and

the channel region is substantially coplanar with the memory layer sequence at the steps.

3. The charge-trapping memory cell as claimed in claim 1, wherein the memory layer sequence comprises sections that extend perpendicularly to a longitudinal channel direction from source to drain.

4. The charge-trapping memory cell as claimed in claim 1, wherein the upper and lower confinement layers comprise oxide layers and the memory layer comprises a nitride layer.

5. The charge-trapping memory cell as claimed in claim 1, wherein the semiconductor body comprises a semiconductor substrate.

6. The charge-trapping memory cell as claimed in claim 1, wherein the semiconductor body comprises a semiconductor layer.

7. A charge-trapping memory cell, comprising:

a semiconductor body with a main surface;

a source region, a channel region and a drain region arranged at the main surface;

a memory layer sequence of dielectric materials provided for charge-trapping, the memory layer sequence comprising a lower confinement layer, a memory layer and an upper confinement layer;

wherein the memory layer sequence is arranged at least adjacent to junctions between the source region and the channel region and between the drain region and the channel region;

a gate electrode being arranged above the channel region and electrically insulated from the semiconductor body; and

wherein the source region and the drain region are slightly recessed with respect to the channel region, the memory layer sequence being arranged at both ends of the channel region with respect to a longitudinal direction extending from source to drain.

8. The charge-trapping memory cell as claimed in claim 7, wherein the channel region and the recessed source and drain regions form steps in the main surface and wherein the steps are covered with the memory layer sequence.

9. The charge-trapping memory cell as claimed in claim 8, wherein the gate electrode covers the channel region and the steps in the main surface.

10. The charge-trapping memory cell as claimed in claim 9, wherein the gate electrode covers the channel region and at least areas of the source region and the drain region.

11. The charge-trapping memory cell as claimed in claim 7, wherein the gate electrode covers the channel region and at least areas of the source region and the drain region.

12. The charge-trapping memory cell as claimed in claim 7, wherein the upper and lower confinement layers comprise oxide layers and the memory layer comprises a nitride layer.

13. A method of forming a charge-trapping memory cell, the method comprising:

providing a semiconductor body;

forming a channel region at a main surface of the semiconductor body;

forming source and drain regions in the semiconductor body adjacent the channel region such that the source region is spaced from the drain region by the channel region, wherein an upper surface of the channel region is located in a plane that is laterally elevated relative to a plane of an upper surface of the source and drain regions;

forming a memory layer sequence overlying the channel region and at least portions of the source and drain regions adjacent the channel region, the memory layer sequence including a lower confinement layer, a memory layer and an upper confinement layer; and

forming a gate overlying the memory layer sequence.

14. The method of claim 13 wherein a junction between the source region and the channel region is located at a first step and wherein a junction between the source region and the channel region is located at a second step, and wherein the memory layer sequence overlies the first step and the second step.

15. The method of claim 14 wherein the first step comprises a vertical sidewall of the semiconductor body and wherein the second step comprises a vertical sidewall of the semiconductor body.

16. A method of operating a semiconductor device, the method comprising:

providing a semiconductor body with a substantially planar upper surface;

causing carriers to travel through the semiconductor body in a direction substantially parallel to the upper surface; and

causing the carriers to continue travelling in the direction substantially parallel to the upper surface so that the carriers travel through a sidewall of the semiconductor body, through a confinement layer and into a memory storage layer.

17. The method of claim 16 wherein the carriers comprise electrons.

18. The method of claim 16 wherein the carriers are caused to travel through a sidewall that is substantially perpendicular to the upper surface.

19. The method of claim 16 wherein causing the carriers to travel and causing the carriers to continue travelling comprises causing the carriers to travel in a substantially straight line.

20. The method of claim 16 wherein the confinement layer and memory storage layer comprise dielectric layers.