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Charge-trapping memory cell

  • US 20060067122A1
  • Filed: 09/29/2004
  • Published: 03/30/2006
  • Est. Priority Date: 09/29/2004
  • Status: Abandoned Application
First Claim
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1. A charge-trapping memory cell, comprising:

  • a semiconductor body with a main surface;

    a source region, a channel region and a drain region disposed at the main surface, the source region being spaced from the drain region by the channel region, wherein the source region and the drain region are doped to have the same conductivity type;

    a memory layer sequence of dielectric materials provided for charge-trapping and comprising a lower confinement layer, a memory layer and an upper confinement layer, the memory layer sequence being arranged on the main surface at least in areas that cover junctions between the source region and the channel region and between the drain region and the channel region, wherein main surface is structured so that a plane formed by the main surface in the area of the channel region intersects the memory layer sequence; and

    a gate electrode arranged adjacent the memory layer sequence and provided to control the channel.

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