Adaptive delay base loss equalization

• US 20060067398A1
• Filed: 09/30/2004
• Published: 03/30/2006
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ruff, Klaus, Chaudhuri, Santanu, Shykind, David, McCall, James A.
• Granted Patent: US 9,219,623 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: H04L 2025/03751 only once, at installation H04L2025/03738 takes precedence
• CPC Class Codes: H04L 25/0224 using sounding signals
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

Claims

1. A method comprising:

self-determining in an initiator equalization parameter for a channel between the initiator and a,responder; and

setting the equalization parameter to have the value.

2. The method of claim 1 wherein self-determining comprises:

determining a delay for a signal on the channel between the initiator and the responder.

3. The method of claim 2 wherein determining comprises:

transmitting an equalization insensitive signal from the initiator to the responder;

initiating a count concurrently with transmitting;

receiving a returned equalization insensitive response signal; and

terminating the count.

4. The method of claim 3 comprises:

initializing the initiator and the responder for a delay calculation before transmitting the signal.

5. The method of claim 3 wherein self-determining further comprises:

indexing into a lookup table based on the count.

6. The method of claim 3 wherein transmitting comprises:

generating a step signal.

7. The method of claim 2 wherein self-determining further comprises:

calculating the equalization parameter from the delay determined.

8. The method of claim 3 wherein determining further comprises:

subtracting a defined number of cycles from the count for responder processing time.

9. The method of claim 3 further comprising:

transmitting a forwarded clock concurrently with the equalization insensitive signal.

10. An apparatus comprising:

a signal generator to generate an equalization insensitive signal;

a transmitter to transmit the signal on a first link;

a receiver to receive a response signal on a second link;

a counter to maintain a count between a transmission of the signal and a receipt of the response signal; and

logic to set an equalization parameter based on the count.

11. The apparatus of claim 10 further comprising:

a lookup table to provide the equalization parameter based on the count.

12. The apparatus of claim 10 wherein the first link is an outgoing link of a channel and the second link is a return link of the channel.

13. The apparatus of claim 10 further comprising:

an arithmetic unit to reduce the count by a value corresponding to a responder processing time.

14. A system comprising:

a motherboard;

a processor to self-determine an equalization parameter for channel or which the processor communicates, the processor coupled to the motherboard;

a chipset coupled to the motherboard, the motherboard defining a first channel between the chipset and the processor;

a memory coupled to the motherboard; and

the motherboard defining a second channel between the memory and the chipset.

15. The system of claim 14 wherein the chipset comprises:

logic to self-determine an equalization parameter for the second channel.

16. The system of claim 14 wherein the processor and the chipset each comprise:

a signal generates to generate an equalization insensitive signal; and

a counter to determine a delay from transmission of the equalization insensitive signal to receipt of a response signal.

17. The system of claim 14 wherein the processor comprises:

logic to determine a round trip signal delay on the first channel; and

a lookup table indexed by the delay to identify the equalization parameter.

18. The system of claim 14 wherein the first channel comprises:

a plurality of link elements of different lengths and wherein the equalization parameter is determined from a delay on the longest link element of the channel.