Semiconductor circuit device

• US 20060067435A1
• Filed: 09/07/2005
• Published: 03/30/2006
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ogawa, Jun, Shiraiwa, Mototugu
• Granted Patent: US 7,542,527 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence

Abstract

A semiconductor circuit device is provided which can attain more stable operations against noise in a data communication system without increasing the power consumption of an overall system, thereby improving the reliability of data communication. For a demodulation baseband signal (S11) obtained by performing digital processing on an output signal (S6) from an AD converter (6), the maximum value (S12) and the minimum value (S13) are detected as digital values by a maximum value holding circuit (11) and a minimum value holding circuit (12), an averaging circuit (13) obtains an average value (intermediate value) of the maximum value and the minimum value and detects a frequency offset amount (S14), and the frequency offset amount is fed back to a threshold value of data decision (14), so that binarized demodulation data (S15) is outputted in which the offset of the demodulation baseband signal is corrected.

Claims

1. A semiconductor circuit device for demodulating digital data from a high-frequency signal having a carrier frequency-modulated based on the digital data, comprising:

a digital IQ demodulator for performing quadrature demodulation on a digital signal obtained by digital conversion from an analog signal having been obtained by frequency-converting the high-frequency signal while using an oscillation output of a PLL as a reference frequency signal,

an F-V converter circuit for converting a frequency of a digital output signal from the digital IQ demodulator to a voltage and outputting a demodulation baseband signal corresponding to the digital data after passing the digital output signal through a band-pass filter,

a maximum value holding circuit for holding a maximum value of the demodulation baseband signal outputted from the F-V converter circuit,

a minimum value holding circuit for holding a minimum value of the demodulation baseband signal,

an averaging circuit for averaging the maximum value of the demodulation baseband signal and the minimum value of the baseband signal,

a frequency offset detector for detecting a frequency offset amount on the demodulation baseband signal from the averaging circuit, and

an offset correcting unit for correcting the frequency offset amount on the demodulation baseband signal by using the frequency offset amount as a feedback signal to a threshold value for deciding data of the demodulation baseband signal, the frequency offset amount having been detected by the frequency offset detector.

2. The semiconductor circuit device according to claim 1, further comprising a frequency converter circuit for frequency-converting the frequency offset amount having been detected by the frequency offset detector, and a filter bandwidth correcting unit for correcting a bandwidth of the band-pass filter based on a frequency converted value corresponding to the frequency offset amount having been calculated by the frequency converter circuit.

3. The semiconductor circuit device according to claim 1, further comprising a demodulator offset correcting unit for correcting the frequency offset amount on the demodulation baseband signal for the digital IQ demodulator based on a frequency converted value which has been calculated by a frequency converter circuit and corresponds to the frequency offset amount.

4. The semiconductor circuit device according to claim 1, further comprising a PLL frequency correcting unit for controlling a frequency of an oscillation output of the PLL and correcting the frequency offset amount on the demodulation baseband signal based on a frequency converted value which has been calculated by a frequency converter circuit and corresponds to the frequency offset amount.

5. The semiconductor circuit device according to claim 1, further comprising a feedback gain circuit which provides a given gain for the frequency offset amount having been detected by the frequency offset detector, and uses the frequency offset amount as the feedback signal to the threshold value for deciding the data of the demodulation baseband signal.

6. The semiconductor circuit device according to claim 1, further comprising an operation controller circuit for periodically operating the frequency offset detector, and a timer counter for counting a duty cycle of the frequency offset detector operated by the operation controller circuit.

7. The semiconductor circuit device according to claim 6, further comprising a counting period storage device for storing a set value for setting a counting period of the timer counter at a given value.

8. The semiconductor circuit device according to claim 7, further comprising a frequency offset value storage device for storing the frequency offset value having been detected by the frequency offset detector, and an operation controller circuit for exercising control to update a value of the frequency offset value storage device with a given period.

9. The semiconductor circuit device according to claim 8, further comprising a comparator for comparing the frequency offset value having been stored in the frequency offset value storage device and the frequency offset value currently detected by the frequency offset detector, and a unit for deciding a change in the frequency offset value based on a comparison result of the comparator, causing the counting period storage device to store a count set value of the timer counter according to a decision result, and changing the duty cycle of the frequency offset detector operated by the operation controller circuit.

10. The semiconductor circuit device according to claim 9, further comprising an operation controller circuit for generating a control signal for controlling update of the frequency offset value, the control signal being generated according to a moving direction and a movement amount decided based on a code of the frequency offset value in the comparison result of the comparator.

11. The semiconductor circuit device according to claim 6, further comprising an F detector circuit for deciding a period of the timer counter, and a bit mask circuit for masking specific bits of the demodulation baseband signal according to the period decided by the F detector circuit.