Memory cell and method for forming the same

• US 20060068548A1
• Filed: 11/10/2005
• Published: 03/30/2006
• Est. Priority Date: 06/21/2002
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Kris K. Brown
• Inventors: Brown, Kris K.
• Granted Patent: US 7,324,367 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor memory cell structure having 4 F² dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Claims

1-25. -25. (canceled)

26. A memory device having an address bus and a data terminal, comprising:

an array of memory cells formed on a substrate having a surface, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;

a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;

a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and

a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein a plurality of memory cells of the array of memory cells comprises;

an active region formed in the substrate;

a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;

a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;

a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and

a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.

27. The memory device of claim 26 wherein each contact of the plurality of contacts is formed over a respective portion of the active region that extends laterally on the surface of the substrate from a respective region between a pair of posts.

28. The memory device of claim 26 wherein each contact of the plurality of contacts is formed adjacent a respective one of the regions for the pair of posts and equidistant from each of the posts of the pair.

29. The memory device of claim 26 wherein each contact of the plurality of contacts comprises a contact having a first portion formed adjacent a respective one of the regions for a pair of posts and further having a second portion formed in the region between the pair of posts.

30. The memory device of claim 26 wherein the active region formed in the substrate comprises an active region extending laterally across the surface of the substrate and the plurality of posts formed over the active region comprises at least three posts.

31. The memory device of claim 26 wherein each post of the plurality of posts comprises a post formed from a doped epitaxial silicon material.

32. The memory device of claim 26 wherein each post of the plurality of posts comprises a post having first and second opposite lateral surfaces and each gate structure of the plurality of gate structures is formed adjacent to the first and second opposite lateral surfaces of the respective post.

33. The memory device of claim 26 wherein each post of the plurality of posts comprises a post having first and second adjacent lateral surfaces and each gate structure of the plurality of gate structures is formed adjacent to the first and second adjacent lateral surfaces of the respective post.

34. The memory device of claim 26 wherein each memory cell capacitor of the plurality of memory cell capacitors comprises a container-shaped capacitor structure.

35. A memory device having an address bus and a data terminal, comprising:

an array of memory cells formed on a substrate having a surface, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;

a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;

a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and

a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell of the array of memory cells comprises;

an active region formed in the substrate;

a semiconductor post formed on the active region;

first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;

a memory cell capacitor formed on the semiconductor post; and

a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated.

36. The memory device of claim 35 wherein the first and second contacts are formed equidistant from the semiconductor post.

37. The memory device of claim 35 wherein the first and second contacts are formed from a titanium material.

38. The memory device of claim 35 wherein the first and second contacts are formed from a tungsten material.

39. The memory device of claim 35 wherein the first and second contacts are formed from a metal material.

40. The memory device of claim 35 wherein the memory cell capacitor comprises:

a first capacitor plate layer formed from a first material;

a second capacitor plate layer formed from a second material; and

a dielectric layer disposed between the first and second capacitor plate layers.

41. The memory device of claim 40 wherein the dielectric layer comprises a layer of aluminum oxide.

42. The memory device of claim 40 wherein the dielectric layer comprises a layer of hafnium oxide.

43. The memory device of claim 40 wherein the first and second plates are formed from the same material.

44. The memory device of claim 40 wherein the first and second plates are formed from a titanium material

45. The memory device of claim 40 wherein the first and second plates are formed from a tantalum material

46. The memory device of claim 40 wherein the first and second plates are formed from a platinum material

47. The memory device of claim 35 wherein the gate of the vertical access transistor is formed from a titanium material.

48. The memory device of claim 35 wherein the gate of the vertical access transistor is formed from a molybdenum material.

49. The memory device of claim 35 wherein the gate of the vertical access transistor is formed from a nickel material.

50. The memory device of claim 35 wherein the gate of the vertical access transistor is formed from a silicon material.

51. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising;

an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;

a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;

a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and

a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein a plurality of memory cells of the array of memory cells comprises;

an active region formed in the substrate;

a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;

a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;

a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and

a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.

52. The computer system of claim 51 wherein each contact of the plurality of contacts is formed over a respective portion of the active region that extends laterally on the surface of the substrate from a respective region between a pair of posts.

53. The computer system of claim 51 wherein each contact of the plurality of contacts is formed adjacent a respective one of the regions for the pair of posts and equidistant from each of the posts of the pair.

54. The computer system of claim 51 wherein each contact of the plurality of contacts comprises a contact having a first portion formed adjacent a respective one of the regions for a pair of posts and further having a second portion formed in the region between the pair of posts.

55. The computer system of claim 51 wherein the active region formed in the substrate comprises an active region extending laterally across the surface of the substrate and the plurality of posts formed over the active region comprises at least three posts.

56. The computer system of claim 51 wherein each post of the plurality of posts comprises a post formed from a doped epitaxial silicon material.

57. The computer system of claim 51 wherein each post of the plurality of posts comprises a post having first and second opposite lateral surfaces and each gate structure of the plurality of gate structures is formed adjacent to the first and second opposite lateral surfaces of the respective post.

58. The computer system of claim 51 wherein each post of the plurality of posts comprises a post having first and second adjacent lateral surfaces and each gate structure of the plurality of gate structures is formed adjacent to the first and second adjacent lateral surfaces of the respective post.

59. The computer system of claim 51 wherein each memory cell capacitor of the plurality of memory cell capacitors comprises a container-shaped capacitor structure.

60. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising;

an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;

a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;

a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and

a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell of the array of memory cells comprises;

an active region formed in the substrate;

a semiconductor post formed on the active region;

first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;

a memory cell capacitor formed on the semiconductor post; and

a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated.

61. The computer system of claim 60 wherein the first and second contacts are formed equidistant from the semiconductor post.

62. The computer system of claim 60 wherein the first and second contacts are formed from a titanium material.

63. The computer system of claim 60 wherein the first and second contacts are formed from a tungsten material.

64. The computer system of claim 60 wherein the first and second contacts are formed from a metal material.

65. The computer system of claim 60 wherein the memory cell capacitor comprises:

a first capacitor plate layer formed from a first material;

a second capacitor plate layer formed from a second material; and

a dielectric layer disposed between the first and second capacitor plate layers.

66. The computer system of claim 65 wherein the dielectric layer comprises a layer of aluminum oxide.

67. The computer system of claim 65 wherein the dielectric layer comprises a layer of hafnium oxide.

68. The computer system of claim 65 wherein the first and second plates are formed from the same material.

69. The computer system 6f claim 65 wherein the first and second plates are formed from a titanium material

70. The computer system of claim 65 wherein the first and second plates are formed from a tantalum material

71. The computer system of claim 65 wherein the first and second plates are formed from a platinum material

72. The computer system of claim 60 wherein the gate of the vertical access transistor is formed from a titanium material.

73. The computer system of claim 60 wherein the gate of the vertical access transistor is formed from a molybdenum material.

74. The computer system of claim 60 wherein the gate of the vertical access transistor is formed from a nickel material.

75. The computer system of claim 60 wherein the gate of the vertical access transistor is formed from a silicon material.

76-100. -100. (canceled)