Method for chip singulation

• US 20060068567A1
• Filed: 09/23/2005
• Published: 03/30/2006
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Swinnen, Bart, Beyne, Eric, Vanhaelemeersch, Serge
• Granted Patent: US 7,566,634 B2
• Time in Patent Office: Days
• US Class Current: 438/460
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304

Abstract

The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

Claims

1. A method of singulating at least one chip from a stack of layers, the stack comprising a front end of line upon a substrate layer, the substrate layer having a first surface and a second surface, the front end of line being positioned on top of the first surface, and a back end of line on top of the front end of line, the method comprising:

etching singulating trenches through the back end of line, through the front end of line and at least partially through the substrate layer of the stack; and

depositing a passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the trenches are at least partially passivated.

2. The method as in claim 1, further comprising:

releasing the at least one chip from the stack of layers.

3. The method as in claim 2, wherein the releasing comprises:

reducing the thickness of the substrate layer from the second surface onwards to the bottom of the etched singulating trenches until the at least one chip is released from the stack.

4. The method as in claim 2, wherein the stack of layers comprises at least two chips, and wherein etching singulating trenches further comprises:

etching two singulating trenches between neighboring chips; and

wherein the releasing comprises dicing between the two etched singulating trenches.

5. The method as in claim 4, wherein the dicing is one of a group consisting of blade dicing, laser dicing and trench etch dicing.

6. The method as in claim 1, further comprising:

positioning metal dummies in the back end of line, wherein the metal dummies are positioned outside a chip area and outside an exclusion zone around the chip area; and

wherein the etching further comprises etching the singulating trenches in the exclusion zone.

7. The method as in claim 1, wherein etching the singulating trenches is performed using back end of line processing technology.

8. The method as in claim 1, wherein etching the singulating trenches further comprises:

etching holes in the area of the at least one chip.

9. The method as in claim 3, further comprising:

performing damascene processing for the back end of line.

10. The method as claim 1, wherein etching the singulating trenches further comprises:

etching the singulating trenches using a mask with a pattern.

11. The method as in claim 10, wherein the pattern corresponds to dies with rounded corners.

12. The method as in claim 1, wherein the back end of line comprises moisture sensitive material.

13. The method as in claim 1, wherein the stack of layers further comprises a metallization layer between the front end of line and the back end of line.

14. The method as in claim 1, wherein the passivation layer comprises multiple sublayers.

15. The method as in claim 1, wherein the depositing is one of physical vapor depositing, chemical vapor depositing and spinning on.

16. The method as in claim 1, further comprising:

attaching the stack of layers to an adhesive film or foil.

17. The method as in claim 1, wherein the substrate layer is one of a silicon substrate, a gallium arsenide substrate and a germanium substrate.

18. The method as in claim 3, wherein the reducing is one of chemical mechanical polishing, grinding and substrate etch backing.

19. A method of singulating at least one chip from a stack of layers, the stack comprising a front end of line upon a substrate layer, the substrate layer having a first surface and a second surface, the front end of line being positioned on top of the first surface, and a back end of line on top of the front end of line, the method comprising:

positioning metal dummies in the back end of line, wherein the metal dummies are positioned outside a chip area and outside an exclusion zone around the chip area; and

etching singulating trenches through the back end of line, through the front end of line and at least partially through the substrate layer of the stack, wherein the etching is done in the exclusion zone.

20. The method as in claim 19, further comprising:

depositing a passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the trenches are at least partially passivated.

21. The method as in claim 19, further comprising:

releasing the at least one chip from the stack of layers.

22. The method as in claim 21, wherein the releasing comprises:

reducing the thickness of the substrate layer from the second surface onwards to the bottom of the etched singulating trenches until the at least one chip is released from the stack.

23. The method as in claim 19, wherein etching the singulating trenches is performed using back end of line processing technology.

24. The method as in claim 19, wherein etching the singulating trenches further comprises:

etching holes in the area of the at least one chip.

25. The method as in claim 22, further comprising:

performing damascene processing for the back end of line.

26. The method as claim 19, wherein etching the singulating trenches further comprises:

etching the singulating trenches using a mask with a pattern.

27. The method as in claim 26, wherein the pattern corresponds to dies with rounded corners.

28. The method as in claim 19, wherein the back end of line comprises moisture sensitive material.

29. The method as in claim 19, wherein the stack of layers further comprises a metallization layer between the front end of line and the back end of line.

30. The method as in claim 20, wherein the passivation layer comprises multiple sublayers.

31. The method as in claim 20, wherein the depositing is one of physical vapor depositing, chemical vapor depositing and spinning on.

32. The method as in claim 19, further comprising:

attaching the stack of layers to an adhesive film or foil.

33. The method as in claim 19, wherein the substrate layer is one of a silicon substrate, a gallium arsenide substrate and a germanium substrate.

34. The method as in claim 22, wherein the reducing is one of chemical mechanical polishing, grinding and substrate etch backing.

35. A method of singulating at least one semiconductor chip from a stack of layers, comprising:

etching singulating trenches through a portion of the stack;

depositing a passivation layer on the stack provided with the etched singulating trenches, such that sidewalls of the singulating trenches are at least partially passivated; and

releasing the at least one semiconductor chip from the stack of layers.