Semiconductor device manufacturing method

• US 20060068572A1
• Filed: 09/14/2005
• Published: 03/30/2006
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okada, Kazuo, Yamada, Hiroshi, Noma, Takashi, Iida, Masanori
• Granted Patent: US 7,413,931 B2
• Time in Patent Office: Days
• US Class Current: 438/577
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

The invention is directed to improvement of reliability of a chip size package type semiconductor device in a manufacturing method thereof. A support body is formed on a front surface of a semiconductor substrate with a first insulation film therebetween. Then, a part of the semiconductor substrate is selectively etched from its back surface to form an opening, and then a second insulation film is formed on the back surface. Next, the first insulation film and the second insulation film at a bottom of the opening are selectively etched, to expose pad electrodes at the bottom of the opening. Then, a third resist layer is selectively formed on a second insulation film at boundaries between sidewalls and the bottom of the opening on the back surface of the semiconductor substrate. Furthermore, a wiring layer electrically connected with the pad electrodes at the bottom of the opening and extending onto the back surface of the semiconductor substrate is selectively formed corresponding to a predetermined pattern.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a first surface and a second surface;

attaching a support body to the first surface;

forming a hole in the semiconductor substrate from the second surface;

forming an insulation film to cover at least part of the second surface, at least part of a sidewall of the hole and at least part of a bottom of the hole;

forming a protection layer to cover at least a portion of the insulation film corresponding to a boundary between the covered sidewall of the hole and the covered bottom of the hole; and

forming a wiring layer that is disposed on the second surface and extends into the hole.

2. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a front surface, a back surface, a first insulation film disposed on the front surface and a pad electrode disposed on the first insulation film;

attaching a support body to the front surface;

forming an opening in the semiconductor substrate and adjacent the pad electrode by etching the semiconductor substrate from the back surface, the opening having a bottom and a sidewall;

forming a second insulation film that is disposed on the back surface and extends into the opening;

etching the first and second insulation films disposed at the bottom of the opening to expose part of the pad electrode;

forming a first protection layer that is disposed on the second surface and extends into the opening so as to cover a portion of the second insulation film corresponding to a boundary between the sidewall and the bottom of the opening; and

forming a wiring layer that is disposed on the back surface and extends into the opening so as to be in contact with the exposed pad electrode, part of the wiring layer being disposed on the first protection layer.

3. The method of claim 2, further comprising forming a second protection layer on the back surface after the forming of the wiring layer and cutting along a dicing line the semiconductor substrate to produce a semiconductor device comprising the pad electrode.

4. The method of claim 3, further comprising forming a conductive terminal on the second protection layer that is connected to the wiring layer.

5. The method of claim 2, wherein the first protection layer comprises a resist layer.