Method for implementation of back-illuminated CMOS or CCD imagers

• US 20060068586A1
• Filed: 09/13/2005
• Published: 03/30/2006
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Pain, Bedabrata
• Granted Patent: US 7,425,460 B2
• Time in Patent Office: Days
• US Class Current: 438/643
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20

Abstract

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Claims

1. A wafer-level process of fabricating an imaging structure, comprising:

providing a wafer comprising an oxide layer buried between silicon wafer and device silicon, the oxide layer adapted to form a passivation layer in the imaging structure;

forming a device layer and interlayer dielectric; and

removing the silicon wafer to expose the oxide layer.

2. The process of claim 1, further comprising:

processing the silicon wafer and device silicon through a bulk-CMOS process flow.

3. The process of claim 2, wherein processing the silicon wafer comprises implantation, oxidation, metal deposition and patterning.

4. The process of claim 1, further comprising:

providing a glass wafer and bonding the interlayer dielectric to the glass wafer.

5. The process of claim 1, further comprising:

attaching on organic substrate to the wafer.

6. The process of claim 1, wherein the silicon wafer is removed through one or more of mechanical grinding, wet etching, or reactive ion etching.

7. The process of claim 1, wherein the silicon wafer is removed using the oxide layer as etch stop.

8. The process of claim 1, wherein the oxide layer is a SiO₂ layer.

9. The process of claim 1, further comprising depositing anti-reflection coating on the exposed oxide layer.

10. The process of claim 9, further comprising a color filter and a microlens on the anti-reflection coating.

11. The process of claim 1, further comprising dicing the wafer into individual dies.

12. A wafer-scale process for fabricating a backside illuminated imager, comprising:

providing a wafer comprising a thermal oxide layer buried between a silicon wafer and device silicon;

forming a device layer;

providing interlayer dielectric to be connected to the device layer;

bonding the interlayer dielectric to a glass wafer;

removing the silicon wafer; and

depositing anti-reflection coating.

13. The process of claim 12, further comprising:

depositing color filter and an array of microlenses on top of the anti-reflection coating.

14. The process of claim 12, wherein the silicon wafer is used as handle wafer for mechanical support during processing of the device layer.

15. The process of claim 12, further comprising providing a substrate.

16. The process of claim 15, wherein the substrate is a glass or organic substrate.

17. The process of claim 15, wherein the substrate provides support during removal of the silicon wafer.

18. The process of claim 12, wherein the thermal oxide layer is made of SiO₂.

19. A combined silicon-on-insulator (SOI) and CMOS process to form an array of imaging devices on a wafer, comprising:

providing a SOI wafer comprising an insulator layer and a device silicon layer;

processing the device silicon layer through a bulk CMOS process flow; and

fabricating the array of imaging devices.

20. The process of claim 19, wherein the device silicon later has a thickness from about 3 μ

m to about 10 μ

m.

21. The process of claim 19, wherein a doping concentration of the device silicon layer is inversely proportional to a thickness of a depletion region of the device silicon layer.

22. The process of claim 19, wherein the imaging devices are isolated therebetween by way of LOCOS or STI structures.

23. The process of claim 19, wherein the wafer comprises an imaging area containing the array of imaging devices and a signal processing area containing CMOS signal processing circuits.