Fabrication of channel wraparound gate structure for field-effect transistor

• US 20060068591A1
• Filed: 09/29/2005
• Published: 03/30/2006
• Est. Priority Date: 09/29/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Radosavljevic, Marko, Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Majumdar, Amlan, Datta, Suman
• Granted Patent: US 7,915,167 B2
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 438/926 Dummy metallization
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Claims

1. A method for fabricating a transistor comprising:

forming a dummy gate over a semiconductor body where the body is disposed on a first dielectric layer;

forming source and drain regions in the body thereby defining a channel region in the body between the source and drain regions;

forming a second dielectric layer over the first dielectric layer;

removing the dummy gate;

seeding the first dielectric layer under the channel region with ions which enhance the etching of the first dielectric layer;

etching the first dielectric layer to define an opening under the channel region in the first dielectric layer; and

forming a gate insulation and a conductive gate surrounding the channel region.

2. The method defined by claim 1, wherein the seeding of the first dielectric layer comprises implanting ions at angle of ±

θ

angle with respect to normal from a wafer on which the fabrication is occurring.

3. The method defined by claim 2, wherein one of the angels θ

is obtained by rotating the wafer by 180°

.

4. The method defined by claim 3, wherein the ions are electrically inactive with respect to the operation of the transistor.

5. The method defined by claim 4, including annealing the transistor after the seeding of the first dielectric layer.

6. The method defined by claim 5, including forming a high-k dielectric layer on the channel regions of the body following the etching of the first dielectric layer.

7. The method defined by claim 1, wherein atomic layer deposition is used for forming the gate insulation and conductive gate.

8. The method defined by claim 7, wherein the gate has a work function between 3.9 to 5.2 eV.

9. The method defined by claim 8, including:

using a first ion implantation of electrically active ions in alignment with a dummy gate to form a tip source and a tip drain region;

forming spacers on sides of the dummy gate;

using a second ion implantation of electrically active ions in alignment with the spacers to form a main source region and a main drain region.

10. A method comprising:

using a replacement gate process to expose a channel region of a transistor body disposed on a dielectric layer;

implanting ions which enhance the etching of the dielectric layer into the dielectric layer underlying the channel region;

etching the dielectric layer; and

forming a gate insulation and gate substantially surrounding the channel region including underlying the channel region.

11. The method defined by claim 10, wherein the ions are implanted at the angles of ±

θ

.

12. The method defined by claim 11, wherein the ions are electrically inert with respect to the operation of the transistor.

13. The method defined by claim 10, wherein the metal gate has a work function of between 3.9 to 5.2 eV.

14. The method defined by claim 10, wherein the replacement gate process includes a polysilicon dummy gate which is removed to expose the channel region.

15. The method defined by claim 14, wherein the ions are implanted at the angles of ±

θ

.

16. The method defined by claim 10, including the annealing of the transistor following the implanting of the ions used to enhance the etching.

17. The method defined by claim 10, wherein the dielectric layer comprises a buried oxide of a silicon-oxide-insulative substrate.

18. The method defined by claim 10, wherein the implanted ions are electrically inert.

19. The method defined by claim 18, wherein the ions are silicon.

20. The method defined by claim 19, wherein the work function of the gate is between 3.9 to 5.2 eV.

21. A method for forming a gate around a three dimensional semiconductor nanostructure comprising:

implanting ions into a surface upon which the nanostructure rests, so as to make the surface more etchable when compared to the nanostructure; and

etching the surface.

22. The method defined by claim 21, including first forming a replacement gate over a channel region of the nanostructure and surrounding the replacement gate with a dielectric.

23. The method defined by claim 22, including removing the replacement gate prior to implanting the ions.