Low noise filter for a wireless receiver

• US 20060068749A1
• Filed: 09/25/2004
• Published: 03/30/2006
• Est. Priority Date: 09/25/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Vasa, John E., Ismail, Aly, Ramachandran, Balasubramanian
• Granted Patent: US 7,415,264 B2
• Time in Patent Office: Days
• US Class Current: 455/339
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/45968 by offset reduction
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A low noise filter is arranged to receive an input signal from a downconverter. The low noise filter is constructed to block or cancel any DC offset in the input signal, as well as filter selected frequency components from the input signal. The low noise filter uses a shared capacitor both to handle the DC offset and to set filter response characteristics. As the low noise filter is implemented with a Frequency Dependent Negative Resistance (FDNR) device, the shared capacitor may be relatively small. The low noise filter has a load capacitor, with the output of the load capacitor coupled to a bias resistor and voltage. This bias structure cooperates with the load capacitor to set a high cutoff frequency for the low noise filter useful for blocking or canceling the DC offset.

Claims

1. A low-noise filter for receiving a downconverted signal, comprising:

a signal path extending from an input line to an output line;

a load capacitor in the signal path;

a frequency dependent negative resistance (FDNR) device coupled to the signal path;

a bias resistor coupled to the output of the load capacitor;

a bias voltage source coupled to the bias resistor; and

wherein the bias resistor and the bias voltage are used in setting a high cutoff frequency so that the load capacitor acts to block or cancel a DC offset in the downconverted signal.

2. The low noise filter according to claim 1 wherein the FDNR device is constructed in the form of a Generalized Impedance Component (GIC).

3. The low noise filter according to claim 2 wherein the GIC contributes a pole-pair to the low noise filter'"'"'s transfer function.

4. The low noise filter according to claim 2 further including a resistor between the GIC and the signal path that contributes a zero to the low noise filter'"'"'s transfer function.

5. The low noise filter according to claim 1 further including a second FDNR device coupled to the signal path.

6. The low noise filter according to claim 5 further including an isolation device between the FDNR and the second FDNR.

7. The low noise filter according to claim 1, further including:

a second bias resistor;

a switch connected to one of the bias resistors; and

a control line connected to the switch so that the switched bias resistor is selectively coupled to the load capacitor.

8. A low IF receiver portion having at least one low-noise filter, comprising:

an input line for receiving an RF signal;

a down converter connected to the input line and having a low frequency output line, the down converter coupled to a local oscillator and arranged to generate a low frequency signal on the low frequency output line;

a low-noise filter coupled to the low frequency line, the low noise filter further including a capacitor arrangement and an FDNR device;

a bias resistor cooperating with the capacitor arrangement to form a DC blocking structure; and

an output signal line extending from the low noise filter to a demodulator module.

9. The low IF receiver portion according to claim 8 wherein the down converter is arranged to generate a zero IF signal.

10. The low IF receiver portion according to claim 8 further including:

a filter stage contributing to a transfer function for the low noise filter; and

wherein the capacitor arrangement is shared by the DC blocking structure and the filter stage.

11. A method for filtering, comprising:

providing a baseband signal having unwanted frequency components and a DC offset;

blocking the DC offset using a capacitor; and

filtering the unwanted frequency components using the capacitor.

12. The method according to claim 11, wherein the providing step includes providing a low IF baseband signal.

13. The method according to claim 11, wherein the providing step includes providing a zero IF baseband signal.

14. The method according to claim 11, wherein the blocking step includes:

biasing a bias resistor; and

setting a high-pass cutoff frequency.

15. The method according to claim 11, wherein the filtering step includes having the load capacitor cooperating with a FDNR device.

16. An integrated circuit chip having active and passive components cooperating on a semiconductor substrate to perform a low noise filtering function, comprising:

an input line for receiving a signal;

a capacitor block coupled to the input line and positioned on the integrated circuit chip;

an FDNR device cooperating with the capacitor block to add poles to a transfer function for the low noise filter; and

a bias structure cooperating with the capacitor block to block or cancel DC offset in the signal.

17. The integrated circuit chip according to claim 16, wherein the FDNR device is constructed as a GIC device.

18. The integrated circuit chip according to claim 17, including:

a second GIC device to add poles to the transfer function; and

an isolation device between the GIC and the second GIC.

19. Baseband circuitry, comprising:

an input line for receiving a filtered baseband signal;

control circuitry configured to operate on the filtered baseband signal, wherein the filtered baseband signal is generated according to the steps of;

providing an unfiltered baseband signal having unwanted frequency components and a DC offset;

filtering the unwanted frequency components using an FDNR device that cooperates with a capacitor to define poles in a filter transfer function; and

blocking the DC offset using a capacitor.

20. The baseband circuitry according to claim 19, wherein generating the filtered baseband signal includes using a resistor to define a zero in the filter transfer function;

and the baseband circuitry is constructed to account for nonlinearity introduced by the zero.

21. A low noise filter module for filtering a downconverted signal, comprising:

a signal path extending from an input line to an output line;

a load capacitor on the signal path;

a first filter stage coupled to the signal path and including a first FDNR device;

a second filter stage coupled to the signal path and including a second FDNR device;

bias circuitry coupled to the output of the load capacitor; and

wherein the bias circuitry cooperates with the load capacitor to block or cancel a DC offset in the downconverted signal.

22. The low noise filter module according to claim 21, wherein the first filter stage cooperates with the load capacitor to implement a desired filter transfer function for the low noise filter.

23. The low noise filter module according to claim 21, wherein the load capacitor is constructed to block the DC offset and to define a transfer function.

24. The low noise filter module according to claim 21, wherein the first FDNR device defines a first set of poles in a transfer function and the second FDNR device defines a second set of poles in the transfer function.

25. The low noise filter module according to claim 21, further including a resistor coupled to one of the FDNR devices that defines a zero in a transfer function for the low noise filter.

26. The low noise filter module according to claim 21, further including an isolation device positioned between the first filter stage and the second filter stage.

27. The low noise filter module according to claim 26 wherein the isolation device is constructed as an isolation amplifier.

28. A process for designing a low noise filter, comprising:

selecting a passive filter topology and component values to meet a transfer function requirement, the passive filter having a load resistance, an inductor, and a capacitor;

converting the passive filter to an active filter using a Bruton transformation so that the load resistance is converted to a load capacitance, the inductor is converted to a resistance, and the capacitor is converted to an FDNR device; and

coupling a bias resistor to the output of the load capacitance; and

selecting a bias voltage for the bias resistor that sets a high pass cutoff to block a DC offset.

29. The process according to claim 28, further including selecting impedance scaling and constants for the Bruton transformation that reduce the size of required capacitors.