GPS receiver having RF front end power management and simultaneous baseband searching of frequency and code chip offset

• US 20060068853A1
• Filed: 09/28/2004
• Published: 03/30/2006
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: G2 Microsystems Pty Limited (Microchip Technology Incorporated)
• Original Assignee: G2 Microsystems Pty Limited (Microchip Technology Incorporated)
• Inventors: Single, Peter S., Adams, Andrew, Dejanovic, Thomas
• Granted Patent: US 7,313,421 B2
• Time in Patent Office: Days
• US Class Current: 455/574
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: H04B 1/1607 Supply circuits converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46

Abstract

A GPS receiver includes baseband resources for simultaneous determination of carrier frequency shift and code chip offset. Reduction in the power consumption of a receiver is achieved by managing the sampling rate of an analog-to-digital converter, the intermediate frequency of the RF front end, and the front end bandwidth so these are appropriate to the current function of the receiver. In a GPS receiver during signal tracking, the IF, front end bandwidth, and ADC sampling rate are set as high as possible; during signal acquisition, the IF and front end bandwidth are set to relatively low values, and the ADC sample rate is set to a high value; and during ephemeris download, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values. When a low battery condition is detected, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values regardless of whether the GPS receiver is in the signal acquisition mode, signal tracking mode, or ephemeris download mode.

Claims

1. A receiver with power management, comprising:

an RF front end and a baseband processor;

the RF front end having a bandwidth, and comprising;

a first filter network adapted to receive an RF signal, the first filter network having an output terminal;

a first mixer having a first input terminal coupled to the output terminal of the first filter network;

a first signal source having an output terminal coupled to a second input terminal of the first mixer;

a second filter network, coupled to receive an output signal from the first mixer, the second filter network having an output terminal;

a second mixer having a first input terminal coupled to the output terminal of the second filter network;

a second signal source having an output terminal coupled to a second input terminal of the first mixer;

a third filter network, coupled to receive an output signal from the second mixer, the third filter network having an output terminal; and

an analog-to-digital converter coupled to the output of the third filter network; and

further comprising

control circuitry coupled to the first signal source, and the analog-to-digital converter;

wherein the control circuitry is operable to provide

a first set of control signals such that, the first signal source has a first output frequency, and the analog-to-digital converter has a first sample rate;

a second set of control signals such that the first signal source has a second output frequency, and the analog-to-digital converter has a first sample rate; and

a third set of control signals such that, the first signal source has the first output frequency, and the analog-to-digital converter has a second sample rate.

2. The receiver of claim 1, wherein the first signal source is a local oscillator comprising at least two fixed frequency oscillators, each fixed frequency oscillator having an output selectable in response to one or more signals provided by the control circuitry.

3. The receiver of claim 1, wherein the first signal source is a voltage controlled oscillator having a frequency output that changes responsive to a signal provided by the control circuitry.

4. The receiver of claim 2, wherein the fixed frequency oscillators that are not selected are disconnected from a power supply.

5. The receiver of claim 1, further comprising continuous-time filter circuitry coupled between the third filter network and the analog-to-digital converter.

6. The receiver of claim 5, wherein the continuous-time filter circuitry is coupled to the control circuitry, and is operable to increase and decrease the front end bandwidth responsive to one or more control signals received from the control circuitry.

7. The receiver of claim 6, further comprising digital filter circuitry coupled to the control circuitry and operable to increase and decrease the front end bandwidth responsive to one or more control signals received from the control circuitry.

8. The receiver of claim 1, further comprising circuitry for determining the state of a battery, and communicating the battery state to the control circuitry.

9. A GPS receiver, comprising:

an RF front end including an IF stage and an analog-to-digital converter;

a digital baseband processor coupled to receive a digital baseband signal from the analog-to-digital converter of the RF front end; and

control circuitry coupled to the RF front end and the digital baseband processor;

wherein a frequency of the IF stage is operable to be increased or decreased responsive to the control circuitry, a sample rate of the analog-to-digital converter is operable to be increased or decreased responsive to the control circuitry, and a bandwidth of the RF front end is operable to be increased or decreased responsive to the control circuitry.

10. The GPS receiver of claim 9, wherein during a signal acquisition mode the control circuitry sets the RF front end bandwidth to approximately 2 MHz, the intermediate frequency to approximately 3 MHz, and the ADC sample rate to greater than 10 MHz;

during an ephemeris download mode the control circuitry sets the RF front end bandwidth to approximately 2 MHz, the intermediate frequency to approximately 8 MHz, and the ADC sample rate to approximately 2 MHz.

11. A method of operating a GPS receiver having a front end, and a digital baseband processor, the front end including an IF stage and an ADC, the method comprising:

setting, if in a signal tracking mode, a front end bandwidth to a first value, an IF frequency to a second value, and an ADC sample rate to a third value;

setting, if in a signal acquisition mode, a front end bandwidth to a fourth value, an IF frequency to a fifth value, and an ADC sample rate to a sixth value; and

setting, if in an ephemeris download mode, a front end bandwidth to a seventh value, an IF frequency to an eighth value, and an ADC sample rate to a ninth value.

12. The method of claim 11, wherein the first value represents a front end bandwidth that is at or near the highest possible bandwidth of the front end, and the second value is approximately 8 MHz.

13. The method of claim 11, wherein the fourth value is approximately 2 MHz, the fifth value is approximately 3 MHz, and the sixth value is greater than approximately 10 MHz.

14. The method of claim 13, wherein the seventh value is approximately 2 MHz, the eight value is approximately 3 MHz, and the ninth value is approximately 2 MHz.

15. The method of claim 11, setting an IF frequency comprises changing a local oscillator output frequency that is coupled to a mixer.

16. The method of claim 15, wherein the local oscillator comprises two or more fixed frequency oscillators and selection circuitry coupled thereto to select an output of one of the two or more fixed frequency oscillators, and further comprising powering down the non-selected fixed frequency oscillators.

17. The method of claim 11, further comprising:

determining whether a low battery condition exists; and

setting, if the determination is affirmative, the front end bandwidth to approximately 2 MHz, the IF to approximately 3 MHz, and the ADC sample rate to approximately 2 MHz, regardless of whether the GPS receiver is in signal acquisition mode, signal tracking mode, or ephemeris download mode.

18. The method of claim 11, further comprising:

simultaneously searching for carrier frequency shift and code chip offset.

19. The method of claim 18, wherein simultaneously searching for carrier frequency shift and code chip offset comprises simultaneously multiplying a digitized baseband signal by a plurality of digitally synthesized frequencies, each of the plurality of digitally synthesized frequencies being different from each other;

and concurrently with the multiplying, integrating the result of each multiplication.

20. A method of operating a GPS receiver, comprising:

receiving an incoming signal;

mixing the received signal down to an intermediate frequency signal;

sampling the intermediate frequency signal with an analog-to-digital converter to produce a digitized signal;

programming each one of a plurality of baseband mixers to multiply the digitized signal by one of a plurality of digitally synthesized signals to produce an output signal;

integrating each baseband mixer output signal for a period equal to at least a code chip period;

operating, during the code chip period, a code generator; and

subsequent to the period equal to at least a chip code period, determining whether a peak has been found;

wherein searching for a carrier frequency shift and a code chip offset occur simultaneously.