Multi-processor computer system
First Claim
1. Multi-processor computer system comprising at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1), a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection line (4) for storing a process list of processes to be available for execution by said processors (1), wherein said processors (1) are adapted for loading a global wake-up variable signalling process additions of processes to said process list into their associated cache memory unit (2), for switching into a low-power mode if said process list contains no process for execution by said processors (1) and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.
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Abstract
The present invention relates to a multi-processor computer system comprising at least two processors for parallel execution of processes, at least two cache memory units, each being associated with and connected to a separate processor, a connection bus connecting said processors and said cache memory units, and a process list unit connected to said connection line for storing a process list of processes to be available for execution by said processors. In order to enable power saving if no processes for execution are available while guaranteeing a fast wake-up procedure if such processes are available it is proposed according to the present invention that said processors are adapted for loading a global wake-up variable signalling process additions of processes to said process list into their associated cache memory unit, for switching into a low-power mode if said process list contains no process for execution by said processors and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list. Thus, according to the present invention the cache coherence protocol is used for communicating and signalling the availability of processes for execution.
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Citations
10 Claims
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1. Multi-processor computer system comprising
at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1), a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection line (4) for storing a process list of processes to be available for execution by said processors (1), wherein said processors (1) are adapted for loading a global wake-up variable signalling process additions of processes to said process list into their associated cache memory unit (2), for switching into a low-power mode if said process list contains no process for execution by said processors (1) and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.
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6. Processor for use in a multi-processor computer system comprising
at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1), a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection line (4) for storing a process list of processes to be available for execution by said processors (1), wherein said processor (1) is adapted for loading a global wake-up variable signalling process additions of processes to said process list into its associated cache memory unit (2), for switching into a low-power mode if said process list contains no process for execution by said processor and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.
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7. Method of scheduling the execution of processes in a multi-processor computer system comprising
at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1), a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection line (4) for storing a process list of processes to be available for execution by said processors (1), said method comprising the steps of: -
loading a global wake-up variable signalling process additions of processes to said process list by a processor (1) into its associated cache memory unit (2), adding a process to said process list, and changing the wake-up variable signalling said addition of a process to said process list thus causing said processor (1) to switch from a low-power mode into a normal-power mode. - View Dependent Claims (10)
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8. Method of executing a process by a processor in a multi-processor computer system comprising
at least two processors (1) for parallel execution of processes, at least two cache memory units (2), each being associated with and connected to a separate processor (1), a connection bus (4) connecting said processors (1) and said cache memory units (2), and a process list unit (3) connected to said connection line (4) for storing a process list of processes to be available for execution by said processors (1), said method comprising the steps of: -
loading a global wake-up variable signalling process additions of processes to said process list into an associated cache memory unit (2), switching into a low-power mode if said process list contains no process for execution by said processor (1), switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list, and accessing said process list to get said added process for execution.
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Specification