Cluster PC

• US 20060069806A1
• Filed: 09/08/2004
• Published: 03/30/2006
• Est. Priority Date: 09/08/2004
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Nicoletti, Leonard D. III
• Granted Patent: US 7,877,527 B2
• Time in Patent Office: Days
• US Class Current: 709/245
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: H04L 12/00 Data switching networks interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: H04L 67/02 based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1001 for accessing one among a plurality of replicated servers
• CPC Class Codes: H04L 67/61 taking into account QoS or priority requirements
• CPC Class Codes: H04L 69/14 Multichannel or multilink protocols

Abstract

A computer design based on a platform of multiple central processing units (CPUs). When running multiple applications, each of the multiple CPUs performs all the processing for one of the individual applications. All of the multiple CPUs may operate below the physical layer of the OSI model. They may communicate with each other in a various manners, and they each communicate with a “gateway” CPU that is logically disposed above them on the physical level. The gateway CPU acts as a door or clearinghouse to and from the underground layer. The processing that occurs by the multiple CPUs on the underground layer allows a higher level of security, reliability, and speed compared to conventional single-CPU multitasking systems.

Claims

1. A computer, comprising:

a gateway CPU that communicates with I/O devices or peripherals or both;

a plurality of application-specific CPUs communicating with the gateway CPU, each application-specific CPU running substantially only one application, each of the application-specific CPUs accessing the gateway CPU, or vice-versa, when necessary to access I/O devices or peripherals or both,

such that the gateway CPU substantially acts as a buffer or clearinghouse for data to and from the application-specific CPUs and does not substantially perform application processing itself,

and further comprising at least one connection between one of the application-specific CPUs and another of the application-specific CPUs such that data can be directly transferred from one to another.

2. The computer of claim 1, wherein the connection is a serial or parallel connection.

3. The computer of claim 1, wherein the application-specific CPUs are designed and configured to run specific assigned applications.

4. The computer of claim 1, further comprising multiple connections between respective ones of the application-specific CPUs.

5. The computer of claim 1, wherein each of the application-specific CPUs accesses the gateway CPU according to a predetermined schedule.

6. The computer of claim 1, wherein each of the application-specific CPUs accesses the gateway CPU according to a queue.

7. The computer of claim 1, wherein each of the application-specific CPUs accesses the gateway CPU according to a priority scheme.

8. The computer of claim 3, wherein at least one of the application-specific CPUs are designed and configured to run an application selected from the group consisting of:

word-processing applications, spreadsheet applications, database applications, desktop publishing applications, and internet browsing applications.

9. A method for computing, comprising:

providing a gateway CPU that communicates with I/O devices or peripherals or both;

providing a plurality of application-specific CPUs communicating with the gateway CPU;

running substantially at most one application on each application-specific CPU;

communicating data between one of the application-specific CPUs and another directly without passing the data through the gateway CPU;

wherein the application-specific CPUs accesses the gateway CPU, or vice-versa, when necessary to access I/O devices or peripherals or both,

such that the gateway CPU substantially acts as a buffer or clearinghouse for data to and from the application-specific CPUs and does not substantially perform application processing itself.

10. The method of claim 9, wherein the communicating data step includes communicating data via a serial or parallel connection.

11. The method of claim 9, further comprising designing and configuring the application-specific CPUs to run specific assigned applications.

12. The method of claim 9, wherein the communicating data step further comprises communicating multiple data between multiple application-specific CPUs via multiple connections between respective ones of the application-specific CPUs.

13. The method of claim 9, further comprising accessing the gateway CPU by each of the application-specific CPUs according to a predetermined schedule.

14. The method of claim 9, further comprising accessing the gateway CPU by each of the application-specific CPUs according to a queue.

15. The method of claim 9, further comprising accessing the gateway CPU by each of the application-specific CPUs according to a priority scheme.

16. The method of claim 11, wherein at least one of the application-specific CPUs are designed and configured to run an application selected from the group consisting of:

word-processing applications, spreadsheet applications, database applications, desktop publishing applications, and internet browsing applications.

17. A method for computing, comprising:

providing a gateway CPU that communicates with I/O devices or peripherals or both;

providing a plurality of application-specific CPUs communicating with the gateway CPU;

running substantially at most one application on each application-specific CPU;

wherein the application-specific CPUs accesses the gateway CPU, or vice-versa, when necessary to access I/O devices or peripherals or both,

such that the gateway CPU substantially acts as a buffer or clearinghouse for data to and from the application-specific CPUs and does not substantially perform application processing itself.

18. The method of claim 17, further comprising providing a memory register including plural memory modules, each module in the plurality being provided the same data as written to the memory register, wherein each of the plurality of application-specific CPUs may access a separate module for retrieval of data.

19. The method of claim 18, wherein the providing a memory register includes providing the memory register in hardware.

20. The method of claim 18, wherein the providing a memory register includes providing the memory register in software.

21. The method of claim 18, wherein the providing a memory register includes providing the memory register in a combination of hardware and software.

22. A computer, comprising:

a gateway CPU that communicates with I/O devices or peripherals or both;

a plurality of application-specific CPUs communicating with the gateway CPU, each application-specific CPU running substantially only one application, each of the application-specific CPUs accessing the gateway CPU, or vice-versa, when necessary to access I/O devices or peripherals or both,

such that the gateway CPU substantially acts as a buffer or clearinghouse for data to and from the application-specific CPUs and does not substantially perform application processing itself,

and further comprising at least one memory register for storage of data for the application-specific CPUs, the memory register including plural memory modules, each module in the plurality being provided the same data as written to the memory register, wherein each of the plurality of application-specific CPUs may access a separate module for retrieval of data.

23. The method of claim 22, wherein the memory register is implemented in hardware.

24. The method of claim 22, wherein the memory register is implemented in software.

25. The method of claim 22, wherein the memory register is implemented in a combination of hardware and software.