Deterministic finite automata (DFA) processing
First Claim
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1. A network processor, comprising:
- at least one processor core; and
a deterministic finite automata (DFA) module operating asynchronously to the at least one processor core, the DFA module traversing a plurality of nodes of at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory responsive to instructions from the at least one processor core.
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Abstract
A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.
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Citations
18 Claims
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1. A network processor, comprising:
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at least one processor core; and
a deterministic finite automata (DFA) module operating asynchronously to the at least one processor core, the DFA module traversing a plurality of nodes of at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory responsive to instructions from the at least one processor core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of traversing DFA graphs with incoming packet data, comprising:
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storing at least one DFA graph in a non-cache coherent memory;
storing a DFA instruction in a cache-coherent memory, the DFA instruction indicating packet data stored in the cache-coherent memory to use and the at least one DFA graph stored in the non-cache memory to traverse; and
traversing the DFA graph using the stored packet data and writing intermediate and final results to the cache-coherent memory. - View Dependent Claims (14, 15, 16, 17)
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18. A network processor, comprising:
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means for storing at least one DFA graph in a non-cache coherent memory;
means for storing a DFA instruction in a cache-coherent memory, the DFA instruction indicating packet data stored in the cache-coherent memory to use and the at least one DFA graph stored in the non-cache memory to traverse; and
means for traversing the DFA graph using the stored packet data and writing intermediate and final results to the cache-coherent memory.
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Specification