Measure controlled delay with duty cycle control

• US 20060069940A1
• Filed: 11/15/2005
• Published: 03/30/2006
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Tyler J. Gomm
• Inventors: Gomm, Tyler J.
• Granted Patent: US 7,398,412 B2
• Time in Patent Office: Days
• US Class Current: 713/401
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/4234 being a memory bus

Abstract

The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a delayed input signal, a counter adapted to determine a difference between the input signal and the delayed input signal and produce a coarse timing signal in response thereto, a circuit adapted to produce a fine timing signal based on the input signal, and a circuit adapted to combine the coarse timing signal and the fine timing signal to produce an output signal.

Claims

1. A synchronization circuit adapted to receive an input signal, the synchronization circuit comprising:

a delay monitor adapted to produce a delayed input signal;

a counter adapted to determine a difference between the input signal and the delayed input signal and produce a coarse timing signal in response thereto;

a circuit adapted to produce a fine timing signal based on the input signal; and

a circuit adapted to combine the coarse timing signal and the fine timing signal to produce an output signal.

2. The synchronization circuit of claim 1, wherein the circuit adapted to produce the fine timing signal comprises a ring oscillator and a plurality of latches.

3. The synchronization circuit of claim 2, wherein the latches store a current transition point of the ring oscillator in response to the input signal.

4. The synchronization circuit of claim 2, comprising circuitry adapted to transform data stored in the plurality of latches to produce the fine timing signal.

5. The synchronization circuit of claim 1, wherein the counter is adapted to measure a phase difference between the input signal and the delayed input signal.

6. The synchronization circuit of claim 5, wherein the counter is adapted to measure the period of the input signal.

7. The synchronization circuit of claim 1, wherein the circuit adapted to combine the coarse timing signal and the fine timing signal is an AND gate.

19. The synchronization circuit of claim 1, comprising means for storing a current transition point in a plurality of latches within a ring oscillator in response to the input signal.

20. The synchronization circuit of claim 1, comprising means for transforming data stored in a plurality of latches to produce the fine timing signal.

8. A method comprising:

producing a delayed input signal from an input signal;

determining a difference between the input signal and the delayed input signal;

producing a coarse timing signal based on the difference between the input signal and the delayed input signal;

producing a fine timing signal based on the input signal; and

combining the coarse timing signal and the fine timing signal.

9. The method of claim 8, comprising generating an output based on the combination of the coarse timing signal and the fine timing signal.

10. The method of claim 8, wherein producing the fine timing signal comprises producing the fine timing signal with a ring oscillator and a plurality of latches.

11. The method of claim 10, comprising storing a current transition point in the plurality of latches within the ring oscillator in response to the input signal.

12. The method of claim 10, comprising transforming data stored in the plurality of latches to produce the fine timing signal.

13. The method of claim 8, comprising measuring a phase difference between the input signal and the delayed input signal.

14. The method of claim 8, comprising measuring the period of the input signal.

15. The method of claim 8, wherein combining the coarse timing signal and the fine timing signal comprises combining the coarse timing signal and the fine timing signal with an AND gate.

16. A synchronization circuit comprising:

means for producing a delayed input signal from an input signal;

means for determining a difference between the input signal and the delayed input signal;

means for producing a coarse timing signal based on the difference between the input signal and the delayed input signal;

means for producing a fine timing signal based on the input signal; and

means for combining the coarse timing signal and the fine timing signal.

17. The synchronization circuit of claim 16, comprising means for measuring a phase difference between the input signal and the delayed input signal.

18. The synchronization circuit of claim 16, comprising means for generating an output based on the combination of the coarse timing signal and the fine timing signal.