Field effect trench transistor

• US 20060071276A1
• Filed: 09/20/2005
• Published: 04/06/2006
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Krischke, Norbert, Zundel, Markus, Meyer, Thorsten
• Granted Patent: US 8,772,861 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

One embodiment of the invention relates to a field effect trench transistor with a multiplicity of transistor cells that are arranged like an array and whose gate electrodes are arranged in active trenches formed in a semiconductor body. Inactive trenches are arranged in the array of the transistor cells, there being no gate electrodes situated in said inactive trenches, and a series of polysilicon diodes are integrated in one or more of the inactive trenches which diodes, for protection against damage to the gate oxide through ESD pulses, are contact-connected to a source metallization at one of their ends and to a gate metallization at their other end, and/or alternatively or additionally one or more polysilicon zener diodes connected in series is or are integrated in the inactive trench or trenches and contact-connected to the gate metallization by one of its or their ends and to drain potential by its or their other end.

Claims

1. A field effect trench transistor comprising:

a multiplicity of transistor cells arranged like an array with gate electrodes having a gate oxide and arranged in active trenches that run parallel and are formed in a semiconductor body;

at least one inactive trench running parallel to the active trenches wherein there is no gate electrode arranged in said inactive trench;

one or more polysilicon protective diodes for protection against damage to the gate oxide through ESD pulses being integrated in one or more of the inactive trenches; and

wherein the at least one inactive trench lies in the array of the transistor cells and the plurality of polysilicon protective diodes are connected in series with one another in the longitudinal direction of the respective inactive trench and are contact-connected to a source metallization at one of their ends and to a gate metallization at their other end.

2. The field effect trench transistor of claim 1, wherein every second trench is an inactive trench.

3. The field effect trench transistor of claim 1, wherein the protective diode(s) lie in the trench below the silicon surface of the semiconductor body.

4. The field effect trench transistor of claim 1, wherein the protective diode(s) lie in at least one trench adjacent to a gate pad of the field effect trench transistor and is connected to the gate pad at one of its ends.

5. The field effect trench transistor of claim 4, wherein the protective diode(s) for the case where its p-type implementation zones are not implanted as far as the trench bottom is divided between a plurality of individual shorter trenches lying one behind the other in a series, and mutually facing electrodes of the protective diodes lying in the individual trenches lying one behind the other are contact-connected to one another by an auxiliary metallization above the silicon surface.

6. The field effect trench transistor of claim 1, wherein the trenches above the protective diodes, apart from their contact locations, are filled with insulating oxide up to the silicon surface.

7. The field effect trench transistor of claim 1, wherein the inactive trenches lie parallel to the active trenches.

8. A field effect trench transistor comprising:

a multiplicity of transistor cells arranged like an array with gate electrodes having a gate oxide and arranged in active trenches that run parallel and are formed in a semiconductor body;

at least one inactive trench running parallel to the active trenches, wherein there is no gate electrode arranged in said inactive trench;

one or more polysilicon zener diodes integrated in one or more of the inactive trenches; and

wherein the at least one inactive trench lies in the array of the transistor cells and the plurality of polysilicon zener diodes are connected in series with one another in the longitudinal direction of the respective inactive trench and are contact-connected to a gate metallization by one of their ends and to drain potential by the other end.

9. The field effect trench transistor of claim 8, wherein every second trench is an inactive trench.

10. The field effect trench transistor of claim 8, wherein the zener diode(s) lie in the trench below the silicon surface of the semiconductor body.

11. The field effect trench transistor of claim 9, further including one or more polysilicon protective diodes integrated in one or more of the inactive trenches, wherein the protective diode(s) lie in at least one trench adjacent to a gate pad of the field effect trench transistor and is connected to the gate pad at one of its ends.

12. The field effect trench transistor of claim 11, wherein the protective diode(s) for the case where its p-type implementation zones are not implanted as far as the trench bottom is divided between a plurality of individual shorter trenches lying one behind the other in a series, and mutually facing electrodes of the protective diodes lying in the individual trenches lying one behind the other are contact-connected to one another by an auxiliary metallization above the silicon surface.

13. The field effect trench transistor of claim 12, wherein the trenches above the protective diodes, apart from their contact locations, are filled with insulating oxide up to the silicon surface.

14. The field effect trench transistor of claim 9, wherein the transistor cells directly adjacent to the inactive trenches with the zener diodes are deactivated and equipped with thick oxide in their trenches in order to feed the drain potential to the zener diodes lying alongside without the risk of breakdown.

15. The field effect trench transistor of claim 8, wherein the inactive trenches lie parallel to the active trenches.

16. A field effect trench transistor comprising:

a multiplicity of transistor cells arranged like an array with gate electrodes having a gate oxide and arranged in active trenches that run parallel and are formed in a semiconductor body;

at least one inactive trench running parallel to the active trenches wherein there is no gate electrode arranged in said inactive trench;

means for protecting against damage to the gate oxide through ESD pulses being integrated in one or more of the inactive trenches; and

wherein the at least one inactive trench lies in the array of the transistor cells and the plurality of polysilicon protective diodes are connected in series with one another in the longitudinal direction of the respective inactive trench and are contact-connected to a source metallization at one of their ends and to a gate metallization at their other end.

17. The field effect trench transistor of claim 16, wherein every second trench is an inactive trench.

18. The field effect trench transistor of claim 16, wherein the means for protecting further include a plurality of polysilicon protective diodes.

19. The field effect trench transistor of claim 18, wherein the protective diode(s) lie in the trench below the silicon surface of the semiconductor body.

20. The field effect trench transistor of claim 18, further including one or more polysilicon zener diodes integrated in one or more of the inactive trenches.