Power led package
First Claim
1. A chip package comprising:
- an electrically insulating substrate having a front principal side;
planar first and second electrical power buses each having a chip bonding portion and a lead portion extending away from the chip bonding portion, at least the chip bonding portions of the first and second electrical power buses being disposed on the front principal side of the substrate and having edges spaced apart from one another to define an extended electrical isolation gap; and
a plurality of chips straddling the extended electrical isolation gap and electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses.
1 Assignment
0 Petitions
Accused Products
Abstract
In a chip package (10, 10′, 110, 210), first and second electrical power buses (14, 14′, 16, 16′, 114, 116, 214, 216) are each formed of an electrical conductor having a chip bonding portion (20, 22, 120, 122, 220, 222) and a lead portion (26, 26′, 28, 28′, 126, 128, 226, 228) extending away from the chip bonding portion. The chip bonding portions of the first and second electrical power buses have edges (32, 34, 132, 134, 232, 234) spaced apart from one another to define an extended electrical isolation gap (40, 140, 240). A plurality of chips (42, 44, 46, 142, 143, 144, 145, 146, 147, 148, 242) straddle the extended electrical isolation gap and are electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses.
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Citations
24 Claims
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1. A chip package comprising:
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an electrically insulating substrate having a front principal side;
planar first and second electrical power buses each having a chip bonding portion and a lead portion extending away from the chip bonding portion, at least the chip bonding portions of the first and second electrical power buses being disposed on the front principal side of the substrate and having edges spaced apart from one another to define an extended electrical isolation gap; and
a plurality of chips straddling the extended electrical isolation gap and electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A chip package comprising:
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first and second electrical power buses each formed of an electrical conductor having a chip bonding portion and a lead portion extending away from the chip bonding portion, the chip bonding portions of the first and second electrical power buses having edges spaced apart from one another to define an extended electrical isolation gap; and
a plurality of chips straddling the extended electrical isolation gap and electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A chip operating method comprising:
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forming first and second electrical power buses each having a chip bonding portion and a lead portion extending away from the chip bonding portion;
disposing at least the chip bonding portions of the formed first and second electrical power buses on a front principal side of an electrically insulating substrate with edges of the chip bonding portions arranged spaced apart from one another to define an extended electrical isolation gap; and
bonding a plurality of chips across the extended electrical isolation gap and electrically connected with the first and second electrical power buses to receive electrical operating power via the first and second electrical power buses. - View Dependent Claims (22, 23, 24)
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Specification