Face-to-face bonded I/O circuit die and functional logic circuit die system

• US 20060071332A1
• Filed: 09/29/2004
• Published: 04/06/2006
• Est. Priority Date: 09/29/2004
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Speers, Theodore
• Granted Patent: US 7,459,772 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-to-face bonding pads of each member of the other set.

Claims

1. An integrated circuit system including:

a first integrated circuit die having input/output circuits disposed thereon;

a second integrated circuit die having logical function circuits disposed thereon; and

said first and second integrated circuit dice each include an array of mating face-to-face bonding structures disposed on opposing faces thereof and coupled respectively to said input/output circuits and said logical function circuits.

2. The integrated circuit system of claim 1 wherein input/output circuits are disposed in a peripheral portion of said first integrated circuit die and said mating face-to-face bonding pads are disposed on said opposing face of said first integrated circuit die at an interior portion thereof.

3. The integrated circuit system of claim 1 wherein said mating face-to-face bonding pads are disposed at least partially over said input/output circuits.

4. The integrated circuit system of claim 1 further including additional circuits disposed under said mating face-to-face bonding pads.

5. The integrated circuit system of claim 1 wherein said logical function circuits on said second integrated circuit die include a field programmable gate array.

6. The integrated circuit system of claim 5 further including additional circuits disposed under said mating face-to-face bonding pads.

7. The integrated circuit system of claim 6 wherein said additional circuits include a digital-to-analog converter circuit.

8. The integrated circuit system of claim 6 wherein said additional circuits include an analog-to-digital converter circuit.

9. The integrated circuit system of claim 6 wherein said additional circuits include a voltage-regulator circuit.

10. The integrated circuit system of claim 6 wherein said additional circuits include a field-programmable-gate-array programming-control circuit.

11. The integrated circuit system of claim 6 wherein said additional circuits include at least one charge-pump circuit.

12. The integrated circuit system of claim 6 wherein said additional circuits include a data-conditioning circuit.

13. The integrated circuit system of claim 12 wherein said data-conditioning circuit comprises a serdes circuit.

14. The integrated circuit system of claim 13 wherein said data-conditioning circuit comprises a bus-interface circuit.

15. An input/output integrated circuit for use in an integrated-circuit system including:

a plurality of input/output circuits disposed thereon;

an array of face-to-face bonding pads disposed on a face thereof and coupled to said input/output circuits, said array being arranged in a match pattern.

16. A functional integrated circuit for use in an integrated-circuit system including:

at least one functional circuit disposed thereon;

an array of face-to-face bonding pads disposed on a face thereof and coupled to said functional circuit, said array being arranged in a match pattern.

17. An integrated circuit system including:

a set of first integrated circuit die having input/output circuits disposed thereon, each member of the first set having a different configuration of I/O pad connections;

a set of second integrated circuit die having logical function circuits disposed thereon, each member of the second set having a different logical function circuit disposed thereon; and

the first and second sets of integrated circuit dice each include an array of face-to-face bonding structures disposed on opposing faces thereof and coupled respectively to the input/output circuits and the logical function circuits, each array in the first set being disposed in a pattern that matches each array in the second set.

18. The integrated circuit system of claim 17 wherein the configuration of I/O pad connections in the first set comprises a different number of I/O connections.

19. The integrated circuit system of claim 17 wherein the logical function circuit of each logical function circuit in the second set is a programmable logic device and each logical function circuit in the second set includes a different number of gates.