Input/output cells with localized clock routing

• US 20060071691A1
• Filed: 09/30/2004
• Published: 04/06/2006
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Garlepp, Bruno W.
• Granted Patent: US 7,254,797 B2
• Time in Patent Office: Days
• US Class Current: 326/93
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

Described are approaches to routing buffered reference clock signals to a plurality of input/output (I/O) cell instances on an integrated circuit (IC) die. All or a subset of the I/O cell instances include clock routing resources optimized to deliver high-speed, low jitter clock signals within and through the particular instance. The clock routing resources in physically adjacent instances of the input/output cells for a given IC die automatically interconnect, collectively forming clock routing infrastructure optimized for groups of cell instances. This modular approach to clock routing simplifies the task of combining I/O cell instances with other I/O cell instances and with other types of circuitry.

Claims

1. A computer-readable medium having stored thereon a data structure defining circuitry for instantiation on a semiconductor die, the data structure comprising:

a. first data representing a cell defined to include;

i. a clock input port to the cell;

ii. receive circuitry having a clock node;

iii. a first clock path extending from the clock input port to the clock node;

iv. a clock output port from the cell; and

v. a second clock path extending from the clock input port to the clock output port; and

b. second data defining;

i. a first bounding box on the semiconductor die in which to instantiate a first instance of the cell; and

ii. a second bounding box on the semiconductor die in which to instantiate a second instance of the cell, wherein the clock output port of the first instance of the cell is coupled to the clock input port of the second instance of the cell.

2. The computer-readable medium of claim 1, wherein the first data defines the cell to include a clock buffer coupled to the first clock node.

3. The computer-readable medium of claim 2, wherein the first data defines the clock buffer to include a select port adapted to receive a buffer-select signal.

4. The computer-readable medium of claim 1, wherein the second data define a third bounding box on the semiconductor die in which to instantiate a third instance of the cell, and wherein clock output port of the first instance of the cell is coupled to the clock input port of the second instance of the cell via the third instance of the cell.

5. The computer-readable medium of claim 1, wherein the first bounding box is defined to adjoin the second bounding box.

6. The computer-readable medium of claim 1, wherein the first data defines the cell to include a clock buffer disposed between the clock input port and the clock node.

7. The computer-readable medium of claim 6, wherein the clock buffer is disposed between the clock output port and the clock node.

8. The computer-readable medium of claim 7, wherein the first data defines the clock buffer to include a select port adapted to receive a buffer-select signal.

9. A computer-readable medium having stored thereon information describing circuitry, the circuitry comprising:

a. a first cell comprising;

i. a first clock input port;

ii. a first receive circuit having a first clock node;

iii. a first clock path extending from the first clock input port to the first clock node;

iv. a first clock output port; and

v. a second clock path extending from the first clock input port to the first clock output port; and

b. a second cell comprising;

i. a second clock input port;

ii. a second receive circuit having a second clock node;

iii. a third clock path extending from the second clock input port to the second clock node;

iv. a second clock output port; and

v. a fourth clock path extending from the second clock input port to the second clock output port;

vi. wherein the first clock output port is coupled to the second clock input port.

10. The computer-readable medium of claim 9, wherein at least one of the first and second cells further comprises a clock buffer coupled to at least one of the first, second, third and fourth clock paths.

11. The computer-readable medium of claim 9, wherein the circuitry further comprises a first clock buffer and a second clock buffer, the first clock buffer coupled to one of the first and second clock paths and the second clock buffer coupled to one of the third and fourth clock paths.

12. The computer-readable medium of claim 9, wherein the first cell further comprises a first clock buffer coupled to the first clock path and the second cell further comprises a second clock buffer coupled to the third clock path.

13. The computer-readable medium of claim 9, wherein the first cell further comprises a first clock buffer coupled to the second clock path and the second cell further comprises a second clock buffer coupled to the fourth clock path.

14. The computer-readable medium of claim 9, wherein the first cell further comprises a first clock buffer and the second cell further comprises a second clock buffer, and wherein each of the first and second clock buffers include a select port adapted to receive a buffer-select signal.

15. The computer-readable medium of claim 9, wherein the circuitry further comprises a third cell comprising:

a. a third clock input port;

b. a third clock output port;

c. a third receive circuit having a third clock node;

d. a fifth clock path extending from the third clock input port to the third clock output port; and

e. a sixth clock path extending from the third clock input port to the third clock output port;

f. wherein first clock output port is coupled to the second clock input port via the fifth clock path.

16. The computer-readable medium of claim 9, wherein the first cell is adjacent to the second cell.

17. An input/output (I/O) cell for use in combination with a plurality of additional library cells to form a netlist description of an integrated circuit, the input/output cell defined by code comprising:

a. data specifying a clock input port at a first location within a bounding box of the I/O cell;

b. data specifying a clock output port at a second location within the bounding box of the I/O cell, wherein the first location in a first instance of the I/O cell abuts the second location in an abutting second instance of the I/O cell;

c. data specifying a first clock path adapted to convey a clock signal through the I/O cell from the clock input port to the clock output port;

d. data specifying I/O circuitry, including a locked-loop circuit coupled to the clock input port;

e. data specifying a second clock path adapted to convey the clock signal from the clock input port to the I/O circuitry; and

f. data specifying at least one buffer disposed in at least one of the first and second clock paths.

18. The I/O cell of claim 17, wherein the data specifying the at least one buffer specifies the at least one buffer as having a select port.

19. The I/O cell of claim 17, wherein the at least one buffer is disposed between the clock input port and the clock output port.

20. The I/O cell of claim 19, wherein the at least one buffer is disposed between the clock input port and the I/O circuitry.

21. The I/O cell of claim 17, wherein at least one of the additional library cells is a reference clock cell having a reference clock output port at a third location abutting the first location when an instance of the reference clock cell abuts an instance of the I/O cell.

22. The I/O cell of claim 17, wherein the first and second locations overlap in abutting instances of the cell.

23. A computer-readable medium having a netlist description of a circuit, the netlist description suitable for use in a process for forming an integrated circuit on a layer of a semiconductive material, the netlist description comprising:

a. computer-readable code defining a plurality of library cells; and

b. computer-readable code defining at least two input/output (I/O) cell instances, wherein each I/O cell instance comprises;

i. a clock input port at a first location within a bounding box of the I/O cell;

ii. a clock output port at a second location within the bounding box of the I/O cell, wherein the first and second locations abut in abutting instances of the I/O cell;

iii. a first clock path adapted to convey a clock signal through the I/O cell from the clock input port to the clock output port;

iv. I/O circuitry, including a locked-loop circuit coupled to the clock input port;

v. a second clock path adapted to convey the clock signal from the clock input port to the I/O circuitry; and

vi. at least one buffer disposed in at least one of the first and second clock paths.

24. The computer-readable medium of claim 23, wherein the at least one buffer has a select port.

25. The computer-readable medium of claim 23, wherein the at least one buffer is disposed between the clock input port and the clock output port.

26. The computer-readable medium of claim 25, wherein the at least one buffer is disposed between the clock input port and the I/O circuitry.

27. The computer-readable medium of claim 23, wherein at least one of the library cells is a reference clock cell, and wherein an instance of the reference clock cell includes a reference clock output port at a third location abutting the first location when the instance of the reference clock cell abuts one of the instances of the I/O cell.

28. The computer-readable medium of claim 23, wherein the first and second locations overlap in abutting instances of the I/O cell.

29. An integrated circuit comprising:

a. a first cell instance disposed within a first bounding box, the first cell instance including;

i. a first clock input port located within the first bounding box;

ii. a first clock output port located within the first bounding box;

iii. a first buffer located within the first bounding box and having a first buffer input terminal and a first buffer output terminal;

iii. a first conductive strip located within the first bounding box and extending between the first clock input port and the first buffer input terminal;

iv. a second conductive strip located within the first bounding box and extending between the first buffer output terminal and the first clock output port;

v. first locked-loop circuitry located within the first bounding box and having a first clock terminal; and

vi. a third conductive strip located within the first bounding box and extending between the first clock input port and the first clock terminal of the first locked-loop circuitry; and

b. a second cell instance disposed with a second bounding box, the second bounding box located adjacent the first bounding box, the second cell instance comprising the same circuit elements as the first cell instance including;

i. a second clock input port located within the second bounding box;

ii. a second clock output port located within the second bounding box;

iii. a second buffer located within the second bounding box and having a second buffer input terminal and a second buffer output terminal;

iii. a fourth conductive strip located within the second bounding box and extending between the second clock input port and the second buffer input terminal;

iv. a fifth conductive strip located within the second bounding box and extending between the second buffer output terminal and the second clock output port;

v. second locked-loop circuitry located within the second bounding box and having a second clock terminal; and

vi. a sixth conductive strip located within the second bounding box and extending between the second clock input port and the second clock terminal of the second locked-loop circuitry.

30. The integrated circuit of claim 29, wherein at least one of the first and second buffers is disableable.

31. The integrated circuit of claim 30, further comprising a third cell instance adjacent the first cell instance and having a global clock port adapted to receive an external reference clock signal and to derive, from the global reference clock signal, an internal clock signal.

32. The integrated circuit of claim 31, the third cell instance including an internal reference clock node coupled to the first clock input port.

33. The integrated circuit of claim 29, wherein the locked-loop circuitry is a phase-locked loop.

34. The integrated circuit of claim 29, wherein the first and second bounding boxes abut one another.

35. The integrated circuit of claim 29, wherein the first clock output port is coupled to the second clock input port.

36. The integrated circuit of claim 35, wherein the first clock output port is coupled to the second clock input port via a third cell instance having the same circuit elements as the first and second instances.

37. The integrated circuit of claim 29, wherein the third conductive strip within the first bounding box extends between the first clock input port and the first clock terminal of the first locked-loop circuitry via the first buffer.

38. The integrated circuit of claim 37, wherein a sixth conductive strip located within the second bounding box extends between the second clock input port and the second clock terminal of the second locked-loop circuitry via the second buffer.

39. A method of routing a clock path of an integrated circuit, the method comprising:

a. creating a first data structure defining a functional block, the data structure specifying;

i. a clock input port;

ii. a clock output port;

iii. a buffer having a buffer input terminal and a buffer output terminal;

iv. a first conductive strip extending between the clock input port and the buffer input terminal;

v. a second conductive strip extending between the buffer output terminal and the clock output port;

vi. locked-loop circuitry having a clock terminal;

vii. a third conductive strip extending between the clock input port and the clock terminal of the locked-loop circuitry; and

viii. a bounding box encompassing elements i-vii;

b. incorporating the first data structure into a second data structure, the second data structure specifying a first physical location for a first instance of the functional block and a second physical location for a second instance of the functional block;

c. forming the first and second instances on a semiconductor at the specified first and second physical locations; and

d. routing a connection between the clock output port of the first instance and the clock input port of the second instance.

40. The method of claim 39, wherein the first and second instances abut one another.

41. The method of claim 39, further comprising disabling the buffer in at least one of the first and second instances.

42. The method of claim 39, wherein the bounding boxes of the first and second instances overlap one another.

43. The method of claim 39, wherein the third conductor strip extends between the clock input port and the clock terminal of the lock-loop circuitry via the buffer.

44. The method of claim 39, wherein the third conductor strip extends between the clock input port and the clock terminal of the lock-loop circuitry via a second buffer.

45. A method of creating a signal interface with a pre-routed clock path, the method comprising:

a. defining a SerDes cell, comprising a clock input port, a receiver, a clock output port, a first clock path coupled to the clock input port and the receiver, a second clock path coupled to the clock input port and the clock output port, and a buffer disposed on at least one of the first and second clock paths;

b. disposing a plurality of identical instances of the SerDes cell adjacent to one another such that for at least some of the adjacent SerDes cell instances, the clock input port of a first SerDes cell instance is coupled to the clock output port of an adjacent SerDes cell instance.

46. A system for supplying a signal interface with a pre-routed clock path, the system comprising:

a. means for defining a SerDes cell, the cell comprising a clock input port, a receiver, a clock output port, a first clock path coupled to the clock input port and the receiver, a second clock path coupled to the clock input port and the clock output port, and a buffer disposed on at least one of the first and second clock paths; and

b. means for disposing a plurality of identical instances of the SerDes cell adjacent to one another such that for at least some of the adjacent SerDes cell instances, the clock input port of a first SerDes cell instance is coupled to the clock output port of an adjacent SerDes cell instance.