Input/output cells with localized clock routing
First Claim
1. A computer-readable medium having stored thereon a data structure defining circuitry for instantiation on a semiconductor die, the data structure comprising:
- a. first data representing a cell defined to include;
i. a clock input port to the cell;
ii. receive circuitry having a clock node;
iii. a first clock path extending from the clock input port to the clock node;
iv. a clock output port from the cell; and
v. a second clock path extending from the clock input port to the clock output port; and
b. second data defining;
i. a first bounding box on the semiconductor die in which to instantiate a first instance of the cell; and
ii. a second bounding box on the semiconductor die in which to instantiate a second instance of the cell, wherein the clock output port of the first instance of the cell is coupled to the clock input port of the second instance of the cell.
1 Assignment
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Accused Products
Abstract
Described are approaches to routing buffered reference clock signals to a plurality of input/output (I/O) cell instances on an integrated circuit (IC) die. All or a subset of the I/O cell instances include clock routing resources optimized to deliver high-speed, low jitter clock signals within and through the particular instance. The clock routing resources in physically adjacent instances of the input/output cells for a given IC die automatically interconnect, collectively forming clock routing infrastructure optimized for groups of cell instances. This modular approach to clock routing simplifies the task of combining I/O cell instances with other I/O cell instances and with other types of circuitry.
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Citations
46 Claims
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1. A computer-readable medium having stored thereon a data structure defining circuitry for instantiation on a semiconductor die, the data structure comprising:
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a. first data representing a cell defined to include;
i. a clock input port to the cell;
ii. receive circuitry having a clock node;
iii. a first clock path extending from the clock input port to the clock node;
iv. a clock output port from the cell; and
v. a second clock path extending from the clock input port to the clock output port; and
b. second data defining;
i. a first bounding box on the semiconductor die in which to instantiate a first instance of the cell; and
ii. a second bounding box on the semiconductor die in which to instantiate a second instance of the cell, wherein the clock output port of the first instance of the cell is coupled to the clock input port of the second instance of the cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer-readable medium having stored thereon information describing circuitry, the circuitry comprising:
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a. a first cell comprising;
i. a first clock input port;
ii. a first receive circuit having a first clock node;
iii. a first clock path extending from the first clock input port to the first clock node;
iv. a first clock output port; and
v. a second clock path extending from the first clock input port to the first clock output port; and
b. a second cell comprising;
i. a second clock input port;
ii. a second receive circuit having a second clock node;
iii. a third clock path extending from the second clock input port to the second clock node;
iv. a second clock output port; and
v. a fourth clock path extending from the second clock input port to the second clock output port;
vi. wherein the first clock output port is coupled to the second clock input port. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An input/output (I/O) cell for use in combination with a plurality of additional library cells to form a netlist description of an integrated circuit, the input/output cell defined by code comprising:
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a. data specifying a clock input port at a first location within a bounding box of the I/O cell;
b. data specifying a clock output port at a second location within the bounding box of the I/O cell, wherein the first location in a first instance of the I/O cell abuts the second location in an abutting second instance of the I/O cell;
c. data specifying a first clock path adapted to convey a clock signal through the I/O cell from the clock input port to the clock output port;
d. data specifying I/O circuitry, including a locked-loop circuit coupled to the clock input port;
e. data specifying a second clock path adapted to convey the clock signal from the clock input port to the I/O circuitry; and
f. data specifying at least one buffer disposed in at least one of the first and second clock paths. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A computer-readable medium having a netlist description of a circuit, the netlist description suitable for use in a process for forming an integrated circuit on a layer of a semiconductive material, the netlist description comprising:
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a. computer-readable code defining a plurality of library cells; and
b. computer-readable code defining at least two input/output (I/O) cell instances, wherein each I/O cell instance comprises;
i. a clock input port at a first location within a bounding box of the I/O cell;
ii. a clock output port at a second location within the bounding box of the I/O cell, wherein the first and second locations abut in abutting instances of the I/O cell;
iii. a first clock path adapted to convey a clock signal through the I/O cell from the clock input port to the clock output port;
iv. I/O circuitry, including a locked-loop circuit coupled to the clock input port;
v. a second clock path adapted to convey the clock signal from the clock input port to the I/O circuitry; and
vi. at least one buffer disposed in at least one of the first and second clock paths. - View Dependent Claims (24, 25, 26, 27, 28)
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29. An integrated circuit comprising:
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a. a first cell instance disposed within a first bounding box, the first cell instance including;
i. a first clock input port located within the first bounding box;
ii. a first clock output port located within the first bounding box;
iii. a first buffer located within the first bounding box and having a first buffer input terminal and a first buffer output terminal;
iii. a first conductive strip located within the first bounding box and extending between the first clock input port and the first buffer input terminal;
iv. a second conductive strip located within the first bounding box and extending between the first buffer output terminal and the first clock output port;
v. first locked-loop circuitry located within the first bounding box and having a first clock terminal; and
vi. a third conductive strip located within the first bounding box and extending between the first clock input port and the first clock terminal of the first locked-loop circuitry; and
b. a second cell instance disposed with a second bounding box, the second bounding box located adjacent the first bounding box, the second cell instance comprising the same circuit elements as the first cell instance including;
i. a second clock input port located within the second bounding box;
ii. a second clock output port located within the second bounding box;
iii. a second buffer located within the second bounding box and having a second buffer input terminal and a second buffer output terminal;
iii. a fourth conductive strip located within the second bounding box and extending between the second clock input port and the second buffer input terminal;
iv. a fifth conductive strip located within the second bounding box and extending between the second buffer output terminal and the second clock output port;
v. second locked-loop circuitry located within the second bounding box and having a second clock terminal; and
vi. a sixth conductive strip located within the second bounding box and extending between the second clock input port and the second clock terminal of the second locked-loop circuitry. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A method of routing a clock path of an integrated circuit, the method comprising:
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a. creating a first data structure defining a functional block, the data structure specifying;
i. a clock input port;
ii. a clock output port;
iii. a buffer having a buffer input terminal and a buffer output terminal;
iv. a first conductive strip extending between the clock input port and the buffer input terminal;
v. a second conductive strip extending between the buffer output terminal and the clock output port;
vi. locked-loop circuitry having a clock terminal;
vii. a third conductive strip extending between the clock input port and the clock terminal of the locked-loop circuitry; and
viii. a bounding box encompassing elements i-vii;
b. incorporating the first data structure into a second data structure, the second data structure specifying a first physical location for a first instance of the functional block and a second physical location for a second instance of the functional block;
c. forming the first and second instances on a semiconductor at the specified first and second physical locations; and
d. routing a connection between the clock output port of the first instance and the clock input port of the second instance. - View Dependent Claims (40, 41, 42, 43, 44)
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45. A method of creating a signal interface with a pre-routed clock path, the method comprising:
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a. defining a SerDes cell, comprising a clock input port, a receiver, a clock output port, a first clock path coupled to the clock input port and the receiver, a second clock path coupled to the clock input port and the clock output port, and a buffer disposed on at least one of the first and second clock paths;
b. disposing a plurality of identical instances of the SerDes cell adjacent to one another such that for at least some of the adjacent SerDes cell instances, the clock input port of a first SerDes cell instance is coupled to the clock output port of an adjacent SerDes cell instance.
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46. A system for supplying a signal interface with a pre-routed clock path, the system comprising:
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a. means for defining a SerDes cell, the cell comprising a clock input port, a receiver, a clock output port, a first clock path coupled to the clock input port and the receiver, a second clock path coupled to the clock input port and the clock output port, and a buffer disposed on at least one of the first and second clock paths; and
b. means for disposing a plurality of identical instances of the SerDes cell adjacent to one another such that for at least some of the adjacent SerDes cell instances, the clock input port of a first SerDes cell instance is coupled to the clock output port of an adjacent SerDes cell instance.
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Specification